From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59528) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bFTZ9-0002Ol-P2 for qemu-devel@nongnu.org; Tue, 21 Jun 2016 17:50:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bFTZ4-0001E7-Kc for qemu-devel@nongnu.org; Tue, 21 Jun 2016 17:50:38 -0400 Received: from 7.mo1.mail-out.ovh.net ([87.98.158.110]:49490) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bFTZ4-0001Dw-6i for qemu-devel@nongnu.org; Tue, 21 Jun 2016 17:50:34 -0400 Received: from player770.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo1.mail-out.ovh.net (Postfix) with ESMTP id 3EFCCFF9BEF for ; Tue, 21 Jun 2016 23:50:33 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Tue, 21 Jun 2016 23:48:53 +0200 Message-Id: <1466545735-2555-9-git-send-email-clg@kaod.org> In-Reply-To: <1466545735-2555-1-git-send-email-clg@kaod.org> References: <1466545735-2555-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v2 08/10] ppc: Turn a bunch of booleans from int to bool List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org Cc: David Gibson , Alexander Graf , qemu-devel@nongnu.org, Benjamin Herrenschmidt , Cedric Le Goater From: Benjamin Herrenschmidt Signed-off-by: Benjamin Herrenschmidt Reviewed-by: David Gibson Signed-off-by: C=C3=A9dric Le Goater --- target-ppc/translate.c | 37 ++++++++++++++++++------------------- 1 file changed, 18 insertions(+), 19 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index ca7036b22678..83ec2dd7707b 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -192,22 +192,21 @@ struct DisasContext { uint32_t opcode; uint32_t exception; /* Routine used to access memory */ - bool pr, hv, dr; + bool pr, hv, dr, le_mode; bool lazy_tlb_flush; int mem_idx; int access_type; /* Translation flags */ - int le_mode; TCGMemOp default_tcg_memop_mask; #if defined(TARGET_PPC64) - int sf_mode; - int has_cfar; + bool sf_mode; + bool has_cfar; #endif - int fpu_enabled; - int altivec_enabled; - int vsx_enabled; - int spe_enabled; - int tm_enabled; + bool fpu_enabled; + bool altivec_enabled; + bool vsx_enabled; + bool spe_enabled; + bool tm_enabled; ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ int singlestep_enabled; uint64_t insns_flags; @@ -11468,7 +11467,7 @@ void gen_intermediate_code(CPUPPCState *env, stru= ct TranslationBlock *tb) ctx.insns_flags =3D env->insns_flags; ctx.insns_flags2 =3D env->insns_flags2; ctx.access_type =3D -1; - ctx.le_mode =3D env->hflags & (1 << MSR_LE) ? 1 : 0; + ctx.le_mode =3D !!(env->hflags & (1 << MSR_LE)); ctx.default_tcg_memop_mask =3D ctx.le_mode ? MO_LE : MO_BE; #if defined(TARGET_PPC64) ctx.sf_mode =3D msr_is_64bit(env, env->msr); @@ -11479,25 +11478,25 @@ void gen_intermediate_code(CPUPPCState *env, st= ruct TranslationBlock *tb) (env->mmu_model & POWERPC_MMU_64B)) ctx.lazy_tlb_flush =3D true; =20 - ctx.fpu_enabled =3D msr_fp; + ctx.fpu_enabled =3D !!msr_fp; if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) - ctx.spe_enabled =3D msr_spe; + ctx.spe_enabled =3D !!msr_spe; else - ctx.spe_enabled =3D 0; + ctx.spe_enabled =3D false; if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) - ctx.altivec_enabled =3D msr_vr; + ctx.altivec_enabled =3D !!msr_vr; else - ctx.altivec_enabled =3D 0; + ctx.altivec_enabled =3D false; if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { - ctx.vsx_enabled =3D msr_vsx; + ctx.vsx_enabled =3D !!msr_vsx; } else { - ctx.vsx_enabled =3D 0; + ctx.vsx_enabled =3D false; } #if defined(TARGET_PPC64) if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { - ctx.tm_enabled =3D msr_tm; + ctx.tm_enabled =3D !!msr_tm; } else { - ctx.tm_enabled =3D 0; + ctx.tm_enabled =3D false; } #endif if ((env->flags & POWERPC_FLAG_SE) && msr_se) --=20 2.1.4