From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: mark.cave-ayland@ilande.co.uk, aurelien@aurel32.net, thuth@redhat.com
Subject: [Qemu-devel] [PATCH v2 0/3] Second try at fixing sparc register allocation
Date: Tue, 21 Jun 2016 23:52:40 -0700 [thread overview]
Message-ID: <1466578363-12683-1-git-send-email-rth@twiddle.net> (raw)
Attempting to fix the problem reported by Mark re i686 vs sparc64.
Unsurprisingly, the problems tend to revolve around the 6 operand
opcodes like sub2 or qemu_st64, where we use all, or all but one
register.
r~
Richard Henderson (3):
tcg: Fix name for high-half register
tcg: Optimize spills of constants
tcg: Rearrange register allocation
tcg/aarch64/tcg-target.inc.c | 10 ++
tcg/arm/tcg-target.inc.c | 6 +
tcg/i386/tcg-target.inc.c | 21 ++-
tcg/ia64/tcg-target.inc.c | 10 ++
tcg/mips/tcg-target.inc.c | 10 ++
tcg/ppc/tcg-target.inc.c | 6 +
tcg/s390/tcg-target.inc.c | 6 +
tcg/sparc/tcg-target.inc.c | 10 ++
tcg/tcg.c | 409 +++++++++++++++++++++++++++++--------------
tcg/tci/tcg-target.inc.c | 6 +
10 files changed, 351 insertions(+), 143 deletions(-)
--
2.5.5
next reply other threads:[~2016-06-22 6:53 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-22 6:52 Richard Henderson [this message]
2016-06-22 6:52 ` [Qemu-devel] [PATCH v2 1/3] tcg: Fix name for high-half register Richard Henderson
2016-06-22 6:52 ` [Qemu-devel] [PATCH v2 2/3] tcg: Optimize spills of constants Richard Henderson
2016-06-22 6:52 ` [Qemu-devel] [PATCH v2 3/3] tcg: Rearrange register allocation Richard Henderson
2016-06-22 19:00 ` [Qemu-devel] [PATCH v2 0/3] Second try at fixing sparc " Mark Cave-Ayland
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