From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51160) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bFc2J-0001vm-M5 for qemu-devel@nongnu.org; Wed, 22 Jun 2016 02:53:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bFc2G-0006If-HD for qemu-devel@nongnu.org; Wed, 22 Jun 2016 02:53:19 -0400 Received: from mail-qk0-x244.google.com ([2607:f8b0:400d:c09::244]:34266) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bFc2G-0006Ib-Cz for qemu-devel@nongnu.org; Wed, 22 Jun 2016 02:53:16 -0400 Received: by mail-qk0-x244.google.com with SMTP id j2so8048233qkf.1 for ; Tue, 21 Jun 2016 23:53:16 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Tue, 21 Jun 2016 23:52:40 -0700 Message-Id: <1466578363-12683-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v2 0/3] Second try at fixing sparc register allocation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, aurelien@aurel32.net, thuth@redhat.com Attempting to fix the problem reported by Mark re i686 vs sparc64. Unsurprisingly, the problems tend to revolve around the 6 operand opcodes like sub2 or qemu_st64, where we use all, or all but one register. r~ Richard Henderson (3): tcg: Fix name for high-half register tcg: Optimize spills of constants tcg: Rearrange register allocation tcg/aarch64/tcg-target.inc.c | 10 ++ tcg/arm/tcg-target.inc.c | 6 + tcg/i386/tcg-target.inc.c | 21 ++- tcg/ia64/tcg-target.inc.c | 10 ++ tcg/mips/tcg-target.inc.c | 10 ++ tcg/ppc/tcg-target.inc.c | 6 + tcg/s390/tcg-target.inc.c | 6 + tcg/sparc/tcg-target.inc.c | 10 ++ tcg/tcg.c | 409 +++++++++++++++++++++++++++++-------------- tcg/tci/tcg-target.inc.c | 6 + 10 files changed, 351 insertions(+), 143 deletions(-) -- 2.5.5