From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40627) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bFepd-0002KS-Q3 for qemu-devel@nongnu.org; Wed, 22 Jun 2016 05:52:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bFepb-0006I5-GY for qemu-devel@nongnu.org; Wed, 22 Jun 2016 05:52:24 -0400 Received: from mail-lb0-x243.google.com ([2a00:1450:4010:c04::243]:36545) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bFepb-0006Ht-8d for qemu-devel@nongnu.org; Wed, 22 Jun 2016 05:52:23 -0400 Received: by mail-lb0-x243.google.com with SMTP id ur4so3818199lbc.3 for ; Wed, 22 Jun 2016 02:52:23 -0700 (PDT) From: Michael Rolnik Date: Wed, 22 Jun 2016 12:51:50 +0300 Message-Id: <1466589115-57738-6-git-send-email-mrolnik@gmail.com> In-Reply-To: <1466589115-57738-1-git-send-email-mrolnik@gmail.com> References: <1466589115-57738-1-git-send-email-mrolnik@gmail.com> Subject: [Qemu-devel] [PATCH v9 05/10] target-avr: adding AVR interrupt handling List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: rth@twiddle.net, peter.maydell@linaro.org, Michael Rolnik Signed-off-by: Michael Rolnik --- target-avr/helper.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 58 insertions(+), 1 deletion(-) diff --git a/target-avr/helper.c b/target-avr/helper.c index 3e23646..060b2f0 100644 --- a/target-avr/helper.c +++ b/target-avr/helper.c @@ -31,11 +31,68 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - return false; + CPUClass *cc = CPU_GET_CLASS(cs); + AVRCPU *cpu = AVR_CPU(cs); + CPUAVRState *env = &cpu->env; + + bool ret = false; + + if (interrupt_request & CPU_INTERRUPT_RESET) { + if (cpu_interrupts_enabled(env)) { + cs->exception_index = EXCP_RESET; + cc->do_interrupt(cs); + + cs->interrupt_request &= ~CPU_INTERRUPT_RESET; + + ret = true; + } + } + if (interrupt_request & CPU_INTERRUPT_HARD) { + if (cpu_interrupts_enabled(env) && env->intsrc != 0) { + int index = ctz32(env->intsrc); + cs->exception_index = EXCP_INT(index); + cc->do_interrupt(cs); + + env->intsrc &= env->intsrc - 1; /* clear the interrupt */ + cs->interrupt_request &= ~CPU_INTERRUPT_HARD; + + ret = true; + } + } + return ret; } void avr_cpu_do_interrupt(CPUState *cs) { + AVRCPU *cpu = AVR_CPU(cs); + CPUAVRState *env = &cpu->env; + + uint32_t ret = env->pc_w; + int vector = 0; + int size = avr_feature(env, AVR_FEATURE_JMP_CALL) ? 2 : 1; + int base = 0; /* TODO: where to get it */ + + if (cs->exception_index == EXCP_RESET) { + vector = 0; + } else if (env->intsrc != 0) { + vector = ctz32(env->intsrc) + 1; + } + + if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) { + stb_phys(cs->as, env->sp--, (ret & 0x0000ff)); + stb_phys(cs->as, env->sp--, (ret & 0x00ff00) >> 8); + stb_phys(cs->as, env->sp--, (ret & 0xff0000) >> 16); + } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) { + stb_phys(cs->as, env->sp--, (ret & 0x0000ff)); + stb_phys(cs->as, env->sp--, (ret & 0x00ff00) >> 8); + } else { + stb_phys(cs->as, env->sp--, (ret & 0x0000ff)); + } + + env->pc_w = base + vector * size; + env->sregI = 0; /* clear Global Interrupt Flag */ + + cs->exception_index = -1; } int avr_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uint8_t *buf, -- 2.4.9 (Apple Git-60)