From: "Cédric Le Goater" <clg@kaod.org>
To: qemu-ppc@nongnu.org
Cc: David Gibson <david@gibson.dropbear.id.au>,
Alexander Graf <agraf@suse.de>,
qemu-devel@nongnu.org,
Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Cedric Le Goater <clg@kaod.org>
Subject: [Qemu-devel] [PATCH 2/8] ppc: Update LPCR definitions
Date: Mon, 27 Jun 2016 08:55:15 +0200 [thread overview]
Message-ID: <1467010521-6106-3-git-send-email-clg@kaod.org> (raw)
In-Reply-To: <1467010521-6106-1-git-send-email-clg@kaod.org>
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Includes all the bits up to ISA 2.07
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: fixed checkpatch.pl errors ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target-ppc/cpu.h | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index b1354a4791db..c803d672f6e2 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -377,12 +377,16 @@ struct ppc_slb_t {
#define LPCR_VPM1 (1ull << (63 - 1))
#define LPCR_ISL (1ull << (63 - 2))
#define LPCR_KBV (1ull << (63 - 3))
+#define LPCR_DPFD_SHIFT (63 - 11)
+#define LPCR_DPFD (0x3ull << LPCR_DPFD_SHIFT)
+#define LPCR_VRMASD_SHIFT (63 - 16)
+#define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT)
+#define LPCR_RMLS_SHIFT (63 - 37)
+#define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT)
#define LPCR_ILE (1ull << (63 - 38))
-#define LPCR_MER (1ull << (63 - 52))
-#define LPCR_LPES0 (1ull << (63 - 60))
-#define LPCR_LPES1 (1ull << (63 - 61))
#define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */
#define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
+#define LPCR_ONL (1ull << (63 - 45))
#define LPCR_P7_PECE0 (1ull << (63 - 49))
#define LPCR_P7_PECE1 (1ull << (63 - 50))
#define LPCR_P7_PECE2 (1ull << (63 - 51))
@@ -391,6 +395,12 @@ struct ppc_slb_t {
#define LPCR_P8_PECE2 (1ull << (63 - 49))
#define LPCR_P8_PECE3 (1ull << (63 - 50))
#define LPCR_P8_PECE4 (1ull << (63 - 51))
+#define LPCR_MER (1ull << (63 - 52))
+#define LPCR_TC (1ull << (63 - 54))
+#define LPCR_LPES0 (1ull << (63 - 60))
+#define LPCR_LPES1 (1ull << (63 - 61))
+#define LPCR_RMI (1ull << (63 - 62))
+#define LPCR_HDICE (1ull << (63 - 63))
#define msr_sf ((env->msr >> MSR_SF) & 1)
#define msr_isf ((env->msr >> MSR_ISF) & 1)
--
2.1.4
next prev parent reply other threads:[~2016-06-27 6:55 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-27 6:55 [Qemu-devel] [PATCH 0/8] pnv: more fixes to the exception model Cédric Le Goater
2016-06-27 6:55 ` [Qemu-devel] [PATCH 1/8] ppc: Add a bunch of hypervisor SPRs to Book3s Cédric Le Goater
2016-06-27 6:55 ` Cédric Le Goater [this message]
2016-06-27 6:55 ` [Qemu-devel] [PATCH 3/8] ppc: Use a helper to filter writes to LPCR Cédric Le Goater
2016-06-27 6:55 ` [Qemu-devel] [PATCH 4/8] ppc: Fix conditions for delivering external interrupts to a guest Cédric Le Goater
2016-06-27 6:55 ` [Qemu-devel] [PATCH 5/8] ppc: Enforce setting MSR:EE, IR and DR when MSR:PR is set Cédric Le Goater
2016-06-27 6:55 ` [Qemu-devel] [PATCH 6/8] ppc: Initial HDEC support Cédric Le Goater
2016-06-27 6:55 ` [Qemu-devel] [PATCH 7/8] ppc: LPCR is a HV resource Cédric Le Goater
2016-06-27 6:55 ` [Qemu-devel] [PATCH 8/8] ppc: Print HSRR0/HSRR1 in "info registers" Cédric Le Goater
2016-06-28 5:39 ` [Qemu-devel] [PATCH 0/8] pnv: more fixes to the exception model David Gibson
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