From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52334) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHXJ0-00066m-Jp for qemu-devel@nongnu.org; Mon, 27 Jun 2016 10:14:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bHXIz-0000OO-Gk for qemu-devel@nongnu.org; Mon, 27 Jun 2016 10:14:30 -0400 Message-ID: <1467036839.23740.183.camel@aj.id.au> From: Andrew Jeffery Date: Mon, 27 Jun 2016 23:43:59 +0930 In-Reply-To: References: <1466744305-23163-1-git-send-email-andrew@aj.id.au> Content-Type: multipart/signed; micalg="pgp-sha512"; protocol="application/pgp-signature"; boundary="=-0vgj5UzDIWFNF1/PQPD7" Mime-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH v3 0/3] Add ASPEED SCU device List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: =?ISO-8859-1?Q?C=E9dric?= Le Goater , Joel Stanley , QEMU Developers , qemu-arm --=-0vgj5UzDIWFNF1/PQPD7 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, 2016-06-27 at 14:47 +0100, Peter Maydell wrote: > On 24 June 2016 at 05:58, Andrew Jeffery wrote: > >=20 > > Hi all, > >=20 > > These are three patches implementing minimal functionality for the ASPE= ED System > > Control Unit device and integrating it into the AST2400 SoC model/palme= tto-bmc > > machine. The device is critical for initialisation of u-boot and the ke= rnel as > > it provides chip level control registers, influencing the configuration= of the > > software and the software's configuration of the SoC. > >=20 > > Since v2: > >=20 > > * Fix mixing of offsets and register indexes > > * Sanity check device property values > > * SoC actually initialises the silicon revision > >=20 > > Since v1: > >=20 > > * Select reset values based on silicon revision > > * Expose hardware strapping values via properties > >=20 > > Andrew Jeffery (3): > > =C2=A0 hw/misc: Add a model for the ASPEED System Control Unit > > =C2=A0 ast2400: Integrate the SCU model and set silicon revision > > =C2=A0 palmetto-bmc: Configure the SCU's hardware strapping register >=20 >=20 > Applied to target-arm.next, thanks. Thanks; I intend to send a follow-up patch addressing the discussion on patch 3/3. I'm away for a week so it will miss soft-freeze, but given the nature of the patch that might not be the end of the world? Cheers, Andrew --=-0vgj5UzDIWFNF1/PQPD7 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCgAGBQJXcTSnAAoJEJ0dnzgO5LT5X40P/3135kOvuM+yHvdGLFnn3yr3 NtgJRcSOFPkzgpUKdONSG2+XkhlY34R71XXBi85GtMGSdCsSi4b9Dfhzipjc3Ed9 i+hmMgNLJTk0TwceIz/4pfjoANEgn0pmaBcVQ7alYhzDd7RfzthV0dztb4OsBlu6 Jha09lxqtjFQJSvGpsrzoHGdIqmXgBVLzC6pDyH5Bw2ASYIwMxV8St62iiIgW1d7 IF/F9mHfb6nuNScen2r8xVHg38Vtd/FuoNTcTMUPqM/gpyXMxCxA5LV558eIAk30 vJJSGc4uR/JdFle1qUIso6Fr0XEymVBqy3sVXKgxO2NUjsGRXL8Xowv8GXf9yr2F 2lZUZ3j6iC+mt0SdGBqGicHfRr8WGeDHHPVOu3V9tTwXoEfYp+N08McHG7CHm1oj mQxi5TgL1QPeeKsf00sQqXjQZAwJz4QLnPI1XOAtODGj4gJs6H2JvEE+oHzYs+Nr nXPJbavNGQObbRI4ODm6l+F3HQL44Aw3rcXHBLnIQPNn6vzKIct+2DM/0VYb154v zXYlWszyviSLLuVn5tImwuP3kSa3D4F1oVUpDsvCdAKCkAcJaKKCy7VPFEJShR4j NC2ebTkgz8RsLhiqD8WjwWYe0WXXDRB3hSNA4A48+9mNRHIHd3U448YBYW7tHAGg 9dc/UosDIzXD1+nkWZ7N =/eTX -----END PGP SIGNATURE----- --=-0vgj5UzDIWFNF1/PQPD7--