From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 03/18] cadence_gem: Avoid infinite loops with a misconfigured buffer
Date: Mon, 27 Jun 2016 15:44:55 +0100 [thread overview]
Message-ID: <1467038710-24307-4-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1467038710-24307-1-git-send-email-peter.maydell@linaro.org>
From: Alistair Francis <alistair.francis@xilinx.com>
A guest can write zero to the DMACFG resulting in an infinite loop when
it reaches the while(bytes_to_copy) loop.
To avoid this issue enforce a minimum size for the RX buffer. Hardware
does not have this enforcement and relies on the guest to set a non-zero
value.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reported-by: Li Qiang <liqiang6-s@360.cn>
Reported-by: P J P <ppandit@redhat.com>
Message-id: 84bb1c391b833275da3f573d4972920cea34c188.1466539342.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/net/cadence_gem.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 0346f3e..e5f3c98 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -664,6 +664,13 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL;
bytes_to_copy = size;
+ /* Hardware allows a zero value here but warns against it. To avoid QEMU
+ * indefinite loops we enforce a minimum value here
+ */
+ if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) {
+ rxbufsize = GEM_DMACFG_RBUFSZ_MUL;
+ }
+
/* Pad to minimum length. Assume FCS field is stripped, logic
* below will increment it to the real minimum of 64 when
* not FCS stripping
--
1.9.1
next prev parent reply other threads:[~2016-06-27 14:45 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-27 14:44 [Qemu-devel] [PULL 00/18] target-arm queue Peter Maydell
2016-06-27 14:44 ` [Qemu-devel] [PULL 01/18] hw/intc/arm_gicv3: Add missing break Peter Maydell
2016-06-27 14:44 ` [Qemu-devel] [PULL 02/18] cadence_uart: Protect against transmit errors Peter Maydell
2016-06-27 14:44 ` Peter Maydell [this message]
2016-06-27 14:44 ` [Qemu-devel] [PULL 04/18] cadence_gem: Set the last bit when wrap is set Peter Maydell
2016-06-27 14:44 ` [Qemu-devel] [PULL 05/18] arm: Re-enable tmp105 test Peter Maydell
2016-06-27 14:44 ` [Qemu-devel] [PULL 06/18] hw/misc: Add a model for the ASPEED System Control Unit Peter Maydell
2016-06-27 14:44 ` [Qemu-devel] [PULL 07/18] ast2400: Integrate the SCU model and set silicon revision Peter Maydell
2016-06-27 14:45 ` [Qemu-devel] [PULL 08/18] palmetto-bmc: Configure the SCU's hardware strapping register Peter Maydell
2016-06-27 14:45 ` [Qemu-devel] [PULL 09/18] m25p80: Replace JEDEC ID masking with function Peter Maydell
2016-06-27 14:45 ` [Qemu-devel] [PULL 10/18] m25p80: Make a table for JEDEC ID Peter Maydell
2016-06-27 14:45 ` [Qemu-devel] [PULL 11/18] m25p80: Allow more than four banks Peter Maydell
2016-06-27 14:45 ` [Qemu-devel] [PULL 12/18] m25p80: Introduce COLLECTING_VAR_LEN_DATA state Peter Maydell
2016-06-27 14:45 ` [Qemu-devel] [PULL 13/18] m25p80: Add additional flash commands: Peter Maydell
2016-06-27 14:45 ` [Qemu-devel] [PULL 14/18] m25p80: Introduce quad and equad modes Peter Maydell
2016-06-27 14:45 ` [Qemu-devel] [PULL 15/18] m25p80: Introduce configuration registers Peter Maydell
2016-06-27 14:45 ` [Qemu-devel] [PULL 16/18] m25p80: Fast read commands family changes Peter Maydell
2016-06-27 14:45 ` [Qemu-devel] [PULL 17/18] m25p80: New flash devices Peter Maydell
2016-06-27 14:45 ` [Qemu-devel] [PULL 18/18] m25p80: Fix WINBOND fast read command handling Peter Maydell
2016-06-27 15:35 ` [Qemu-devel] [PULL 00/18] target-arm queue Peter Maydell
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