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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 07/18] ast2400: Integrate the SCU model and set silicon revision
Date: Mon, 27 Jun 2016 15:44:59 +0100	[thread overview]
Message-ID: <1467038710-24307-8-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1467038710-24307-1-git-send-email-peter.maydell@linaro.org>

From: Andrew Jeffery <andrew@aj.id.au>

By specifying the silicon revision we select the appropriate reset
values for the SoC.

Additionally, expose hardware strapping properties aliasing those
provided by the SCU for board-specific configuration.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1466744305-23163-3-git-send-email-andrew@aj.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/ast2400.c         | 21 +++++++++++++++++++++
 include/hw/arm/ast2400.h |  2 ++
 2 files changed, 23 insertions(+)

diff --git a/hw/arm/ast2400.c b/hw/arm/ast2400.c
index 4a9de0e..b14a82f 100644
--- a/hw/arm/ast2400.c
+++ b/hw/arm/ast2400.c
@@ -24,9 +24,12 @@
 #define AST2400_IOMEM_SIZE       0x00200000
 #define AST2400_IOMEM_BASE       0x1E600000
 #define AST2400_VIC_BASE         0x1E6C0000
+#define AST2400_SCU_BASE         0x1E6E2000
 #define AST2400_TIMER_BASE       0x1E782000
 #define AST2400_I2C_BASE         0x1E78A000
 
+#define AST2400_A0_SILICON_REV   0x02000303
+
 static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
 static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
 
@@ -72,6 +75,16 @@ static void ast2400_init(Object *obj)
     object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C);
     object_property_add_child(obj, "i2c", OBJECT(&s->i2c), NULL);
     qdev_set_parent_bus(DEVICE(&s->i2c), sysbus_get_default());
+
+    object_initialize(&s->scu, sizeof(s->scu), TYPE_ASPEED_SCU);
+    object_property_add_child(obj, "scu", OBJECT(&s->scu), NULL);
+    qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());
+    qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
+                         AST2400_A0_SILICON_REV);
+    object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
+                              "hw-strap1", &error_abort);
+    object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
+                              "hw-strap2", &error_abort);
 }
 
 static void ast2400_realize(DeviceState *dev, Error **errp)
@@ -110,6 +123,14 @@ static void ast2400_realize(DeviceState *dev, Error **errp)
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
     }
 
+    /* SCU */
+    object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, AST2400_SCU_BASE);
+
     /* UART - attach an 8250 to the IO space as our UART5 */
     if (serial_hds[0]) {
         qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
diff --git a/include/hw/arm/ast2400.h b/include/hw/arm/ast2400.h
index c05ed53..f1a64fd 100644
--- a/include/hw/arm/ast2400.h
+++ b/include/hw/arm/ast2400.h
@@ -14,6 +14,7 @@
 
 #include "hw/arm/arm.h"
 #include "hw/intc/aspeed_vic.h"
+#include "hw/misc/aspeed_scu.h"
 #include "hw/timer/aspeed_timer.h"
 #include "hw/i2c/aspeed_i2c.h"
 
@@ -27,6 +28,7 @@ typedef struct AST2400State {
     AspeedVICState vic;
     AspeedTimerCtrlState timerctrl;
     AspeedI2CState i2c;
+    AspeedSCUState scu;
 } AST2400State;
 
 #define TYPE_AST2400 "ast2400"
-- 
1.9.1

  parent reply	other threads:[~2016-06-27 14:45 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-27 14:44 [Qemu-devel] [PULL 00/18] target-arm queue Peter Maydell
2016-06-27 14:44 ` [Qemu-devel] [PULL 01/18] hw/intc/arm_gicv3: Add missing break Peter Maydell
2016-06-27 14:44 ` [Qemu-devel] [PULL 02/18] cadence_uart: Protect against transmit errors Peter Maydell
2016-06-27 14:44 ` [Qemu-devel] [PULL 03/18] cadence_gem: Avoid infinite loops with a misconfigured buffer Peter Maydell
2016-06-27 14:44 ` [Qemu-devel] [PULL 04/18] cadence_gem: Set the last bit when wrap is set Peter Maydell
2016-06-27 14:44 ` [Qemu-devel] [PULL 05/18] arm: Re-enable tmp105 test Peter Maydell
2016-06-27 14:44 ` [Qemu-devel] [PULL 06/18] hw/misc: Add a model for the ASPEED System Control Unit Peter Maydell
2016-06-27 14:44 ` Peter Maydell [this message]
2016-06-27 14:45 ` [Qemu-devel] [PULL 08/18] palmetto-bmc: Configure the SCU's hardware strapping register Peter Maydell
2016-06-27 14:45 ` [Qemu-devel] [PULL 09/18] m25p80: Replace JEDEC ID masking with function Peter Maydell
2016-06-27 14:45 ` [Qemu-devel] [PULL 10/18] m25p80: Make a table for JEDEC ID Peter Maydell
2016-06-27 14:45 ` [Qemu-devel] [PULL 11/18] m25p80: Allow more than four banks Peter Maydell
2016-06-27 14:45 ` [Qemu-devel] [PULL 12/18] m25p80: Introduce COLLECTING_VAR_LEN_DATA state Peter Maydell
2016-06-27 14:45 ` [Qemu-devel] [PULL 13/18] m25p80: Add additional flash commands: Peter Maydell
2016-06-27 14:45 ` [Qemu-devel] [PULL 14/18] m25p80: Introduce quad and equad modes Peter Maydell
2016-06-27 14:45 ` [Qemu-devel] [PULL 15/18] m25p80: Introduce configuration registers Peter Maydell
2016-06-27 14:45 ` [Qemu-devel] [PULL 16/18] m25p80: Fast read commands family changes Peter Maydell
2016-06-27 14:45 ` [Qemu-devel] [PULL 17/18] m25p80: New flash devices Peter Maydell
2016-06-27 14:45 ` [Qemu-devel] [PULL 18/18] m25p80: Fix WINBOND fast read command handling Peter Maydell
2016-06-27 15:35 ` [Qemu-devel] [PULL 00/18] target-arm queue Peter Maydell

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