From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34863) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHXn0-0002wz-6H for qemu-devel@nongnu.org; Mon, 27 Jun 2016 10:45:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bHXmv-00089i-T4 for qemu-devel@nongnu.org; Mon, 27 Jun 2016 10:45:29 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:57999) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHXmv-000844-Mb for qemu-devel@nongnu.org; Mon, 27 Jun 2016 10:45:25 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1bHXml-0005Sl-Mo for qemu-devel@nongnu.org; Mon, 27 Jun 2016 15:45:15 +0100 From: Peter Maydell Date: Mon, 27 Jun 2016 15:45:00 +0100 Message-Id: <1467038710-24307-9-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1467038710-24307-1-git-send-email-peter.maydell@linaro.org> References: <1467038710-24307-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL 08/18] palmetto-bmc: Configure the SCU's hardware strapping register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: Andrew Jeffery The magic constant configures the following options: * 28:27: Configure DRAM size as 256MB * 26:24: DDR3 SDRAM with CL = 6, CWL = 5 * 23: Configure 24/48MHz CLKIN * 22: Disable GPIOE pass-through mode * 21: Disable GPIOD pass-through mode * 20: Enable LPC decode of SuperIO 0x2E/0x4E addresses * 19: Disable ACPI * 18: Configure 48MHz CLKIN * 17: Disable BMC 2nd boot watchdog timer * 16: Decode SuperIO address 0x2E * 15: VGA Class Code * 14: Enable LPC dedicated reset pin * 13:12: Enable SPI Master and SPI Slave to AHB Bridge * 11:10: Select CPU:AHB ratio = 2:1 * 9:8: Select 384MHz H-PLL * 7: Configure MAC#2 for RMII/NCSI * 6: Configure MAC#1 for RMII/NCSI * 5: No VGA BIOS ROM * 4: Boot using 32bit SPI address mode * 3:2: Select 16MB VGA memory * 1:0: Boot from SPI flash memory Signed-off-by: Andrew Jeffery Reviewed-by: Cédric Le Goater Reviewed-by: Peter Maydell Tested-by: Cédric Le Goater Message-id: 1466744305-23163-4-git-send-email-andrew@aj.id.au Signed-off-by: Peter Maydell --- hw/arm/palmetto-bmc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/palmetto-bmc.c b/hw/arm/palmetto-bmc.c index a51d960..b8eed21 100644 --- a/hw/arm/palmetto-bmc.c +++ b/hw/arm/palmetto-bmc.c @@ -44,6 +44,8 @@ static void palmetto_bmc_init(MachineState *machine) &bmc->ram); object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram), &error_abort); + object_property_set_int(OBJECT(&bmc->soc), 0x120CE416, "hw-strap1", + &error_abort); object_property_set_bool(OBJECT(&bmc->soc), true, "realized", &error_abort); -- 1.9.1