From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47425) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHYJs-0001ly-Nb for qemu-devel@nongnu.org; Mon, 27 Jun 2016 11:19:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bHYJo-0001Dy-F4 for qemu-devel@nongnu.org; Mon, 27 Jun 2016 11:19:28 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:48106) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHYJo-0001DK-8b for qemu-devel@nongnu.org; Mon, 27 Jun 2016 11:19:24 -0400 From: Leon Alrae Date: Mon, 27 Jun 2016 16:19:08 +0100 Message-ID: <1467040752-18666-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH 0/4] target-mips: add extended ASID support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net Currently we assume 8-bit ASID everywhere in target-mips code, whereas MIPS architecture allows greater ASIDs. If CP0.Config4.AE bit is set then EntryHi.ASID is extended to 10 bits. This feature is present in real I6400 CPU therefore implement and enable it in emulated by QEMU I6400 model. This series is based on the patch adding I6400 CPU: https://lists.gnu.org/archive/html/qemu-devel/2016-06/msg07604.html Thanks, Leon Leon Alrae (1): target-mips: enable 10-bit ASIDs in I6400 CPU Paul Burton (3): target-mips: add ASID mask field and replace magic values target-mips: change ASID type to hold more than 8 bits target-mips: support CP0.Config4.AE bit target-mips/cpu.h | 5 ++++- target-mips/helper.c | 10 +++++----- target-mips/machine.c | 10 +++++----- target-mips/op_helper.c | 33 ++++++++++++++++++--------------- target-mips/translate.c | 2 ++ target-mips/translate_init.c | 2 +- 6 files changed, 35 insertions(+), 27 deletions(-) -- 2.7.4