From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47440) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHYJu-0001mp-0d for qemu-devel@nongnu.org; Mon, 27 Jun 2016 11:19:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bHYJt-0001GG-3V for qemu-devel@nongnu.org; Mon, 27 Jun 2016 11:19:29 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:46032) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHYJs-0001G6-Tb for qemu-devel@nongnu.org; Mon, 27 Jun 2016 11:19:29 -0400 From: Leon Alrae Date: Mon, 27 Jun 2016 16:19:11 +0100 Message-ID: <1467040752-18666-4-git-send-email-leon.alrae@imgtec.com> In-Reply-To: <1467040752-18666-1-git-send-email-leon.alrae@imgtec.com> References: <1467040752-18666-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH 3/4] target-mips: support CP0.Config4.AE bit List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net, Paul Burton , James Hogan From: Paul Burton The read-only Config4.AE bit set denotes extended 10 bits ASID. Signed-off-by: Paul Burton Signed-off-by: James Hogan Signed-off-by: Leon Alrae --- target-mips/cpu.h | 1 + target-mips/translate.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 62a149e..3a4720d 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -468,6 +468,7 @@ struct CPUMIPSState { int32_t CP0_Config4_rw_bitmask; #define CP0C4_M 31 #define CP0C4_IE 29 +#define CP0C4_AE 28 #define CP0C4_KScrExist 16 #define CP0C4_MMUExtDef 14 #define CP0C4_FTLBPageSize 8 diff --git a/target-mips/translate.c b/target-mips/translate.c index 01510b3..bab52cb 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -20302,7 +20302,8 @@ void cpu_state_reset(CPUMIPSState *env) if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) { env->CP0_CMGCRBase = 0x1fbf8000 >> 4; } - env->CP0_EntryHi_ASID_mask = 0xff; + env->CP0_EntryHi_ASID_mask = (env->CP0_Config4 & (1 << CP0C4_AE)) ? + 0x3ff : 0xff; env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); /* vectored interrupts not implemented, timer on int 7, no performance counters. */ -- 2.7.4