* [Qemu-devel] [PATCH V4 1/6] tests/acpi: add pxb/pxb-pcie tests
2016-06-30 19:07 [Qemu-devel] [PATCH V4 0/6] pxb: fix 64-bit MMIO allocation Marcel Apfelbaum
@ 2016-06-30 19:07 ` Marcel Apfelbaum
2016-06-30 19:07 ` [Qemu-devel] [PATCH V4 2/6] hw/pxb: declare pxb devices as not hot-pluggable Marcel Apfelbaum
` (5 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Marcel Apfelbaum @ 2016-06-30 19:07 UTC (permalink / raw)
To: qemu-devel; +Cc: marcel, mst, pbonzini, imammedo, lersek, ehabkost
Add an ivshmem device with 4G shared memory to
pxb in order to check the ACPI code of 64bit MMIO allocation.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
---
tests/bios-tables-test.c | 37 +++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/tests/bios-tables-test.c b/tests/bios-tables-test.c
index 92c90dd..3d87f9e 100644
--- a/tests/bios-tables-test.c
+++ b/tests/bios-tables-test.c
@@ -838,6 +838,41 @@ static void test_acpi_piix4_tcg_ipmi(void)
free_test_data(&data);
}
+static void test_acpi_piix4_tcg_pxb(void)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_PC;
+ data.variant = ".pxb";
+ data.required_struct_types = base_required_struct_types;
+ data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types);
+ test_acpi_one("-machine accel=tcg"
+ " -device pxb,id=pxb,bus_nr=0x80,bus=pci.0"
+ " -object memory-backend-file,size=4G,mem-path=/tmp/shmem,share,id=mb"
+ " -device ivshmem-plain,memdev=mb,bus=pxb",
+ &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_q35_tcg_pxb_pcie(void)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_Q35;
+ data.variant = ".pxb_pcie";
+ data.required_struct_types = base_required_struct_types;
+ data.required_struct_types_len = ARRAY_SIZE(ipmi_required_struct_types);
+ test_acpi_one("-machine q35,accel=tcg"
+ " -device pxb-pcie,id=pxb,bus_nr=0x80,bus=pcie.0"
+ " -device ioh3420,id=rp,bus=pxb,slot=1"
+ " -object memory-backend-file,size=4G,mem-path=/tmp/shmem,share,id=mb"
+ " -device ivshmem-plain,memdev=mb,bus=rp",
+ &data);
+ free_test_data(&data);
+}
+
int main(int argc, char *argv[])
{
const char *arch = qtest_get_arch();
@@ -856,6 +891,8 @@ int main(int argc, char *argv[])
qtest_add_func("acpi/q35/tcg/bridge", test_acpi_q35_tcg_bridge);
qtest_add_func("acpi/piix4/tcg/ipmi", test_acpi_piix4_tcg_ipmi);
qtest_add_func("acpi/q35/tcg/ipmi", test_acpi_q35_tcg_ipmi);
+ qtest_add_func("acpi/piix4/tcg/pxb", test_acpi_piix4_tcg_pxb);
+ qtest_add_func("acpi/q35/tcg/pxb-pcie", test_acpi_q35_tcg_pxb_pcie);
}
ret = g_test_run();
boot_sector_cleanup(disk);
--
2.4.3
^ permalink raw reply related [flat|nested] 9+ messages in thread* [Qemu-devel] [PATCH V4 2/6] hw/pxb: declare pxb devices as not hot-pluggable
2016-06-30 19:07 [Qemu-devel] [PATCH V4 0/6] pxb: fix 64-bit MMIO allocation Marcel Apfelbaum
2016-06-30 19:07 ` [Qemu-devel] [PATCH V4 1/6] tests/acpi: add pxb/pxb-pcie tests Marcel Apfelbaum
@ 2016-06-30 19:07 ` Marcel Apfelbaum
2016-06-30 19:07 ` [Qemu-devel] [PATCH V4 3/6] hw/acpi: fix a DSDT table issue when a pxb is present Marcel Apfelbaum
` (4 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Marcel Apfelbaum @ 2016-06-30 19:07 UTC (permalink / raw)
To: qemu-devel; +Cc: marcel, mst, pbonzini, imammedo, lersek, ehabkost
Prevent future issues when hotplug will work for devices
attached to pxbs.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
---
hw/pci-bridge/pci_expander_bridge.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c
index ba320bd..9136a23 100644
--- a/hw/pci-bridge/pci_expander_bridge.c
+++ b/hw/pci-bridge/pci_expander_bridge.c
@@ -308,6 +308,7 @@ static void pxb_dev_class_init(ObjectClass *klass, void *data)
dc->desc = "PCI Expander Bridge";
dc->props = pxb_dev_properties;
+ dc->hotpluggable = false;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
@@ -341,6 +342,7 @@ static void pxb_pcie_dev_class_init(ObjectClass *klass, void *data)
dc->desc = "PCI Express Expander Bridge";
dc->props = pxb_dev_properties;
+ dc->hotpluggable = false;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
--
2.4.3
^ permalink raw reply related [flat|nested] 9+ messages in thread* [Qemu-devel] [PATCH V4 3/6] hw/acpi: fix a DSDT table issue when a pxb is present.
2016-06-30 19:07 [Qemu-devel] [PATCH V4 0/6] pxb: fix 64-bit MMIO allocation Marcel Apfelbaum
2016-06-30 19:07 ` [Qemu-devel] [PATCH V4 1/6] tests/acpi: add pxb/pxb-pcie tests Marcel Apfelbaum
2016-06-30 19:07 ` [Qemu-devel] [PATCH V4 2/6] hw/pxb: declare pxb devices as not hot-pluggable Marcel Apfelbaum
@ 2016-06-30 19:07 ` Marcel Apfelbaum
2016-06-30 19:07 ` [Qemu-devel] [PATCH V4 4/6] acpi: refactor pxb crs computation Marcel Apfelbaum
` (3 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Marcel Apfelbaum @ 2016-06-30 19:07 UTC (permalink / raw)
To: qemu-devel; +Cc: marcel, mst, pbonzini, imammedo, lersek, ehabkost
PXBs do not support hotplug so they don't have a PCNT function.
Since the PXB's PCI root-bus is a child bus of bus 0, the
build_dsdt code will add a call to the corresponding PCNT function.
Fix this by skipping the PCNT call for the above case.
While at it skip also PCIe child buses.
Reported-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
---
hw/i386/acpi-build.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 5a594be..675a3dc 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -596,6 +596,10 @@ static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
QLIST_FOREACH(sec, &bus->child, sibling) {
int32_t devfn = sec->parent_dev->devfn;
+ if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
+ continue;
+ }
+
aml_append(method, aml_name("^S%.02X.PCNT", devfn));
}
}
--
2.4.3
^ permalink raw reply related [flat|nested] 9+ messages in thread* [Qemu-devel] [PATCH V4 4/6] acpi: refactor pxb crs computation
2016-06-30 19:07 [Qemu-devel] [PATCH V4 0/6] pxb: fix 64-bit MMIO allocation Marcel Apfelbaum
` (2 preceding siblings ...)
2016-06-30 19:07 ` [Qemu-devel] [PATCH V4 3/6] hw/acpi: fix a DSDT table issue when a pxb is present Marcel Apfelbaum
@ 2016-06-30 19:07 ` Marcel Apfelbaum
2016-06-30 19:07 ` [Qemu-devel] [PATCH V4 5/6] hw/apci: handle 64-bit MMIO regions correctly Marcel Apfelbaum
` (2 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Marcel Apfelbaum @ 2016-06-30 19:07 UTC (permalink / raw)
To: qemu-devel; +Cc: marcel, mst, pbonzini, imammedo, lersek, ehabkost
Instead of always passing both IO and MEM ranges when
computing CRS ranges, define a new CrsRangeSet structure
that include them both.
This is done before introducing a third type of range,
64-bit MEM, so it will be easier to pass them all around.
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
---
hw/i386/acpi-build.c | 82 ++++++++++++++++++++++++++++++++--------------------
1 file changed, 51 insertions(+), 31 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 675a3dc..eca195d 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -747,6 +747,23 @@ static void crs_range_free(gpointer data)
g_free(entry);
}
+typedef struct CrsRangeSet {
+ GPtrArray *io_ranges;
+ GPtrArray *mem_ranges;
+ } CrsRangeSet;
+
+static void crs_range_set_init(CrsRangeSet *range_set)
+{
+ range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
+ range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
+}
+
+static void crs_range_set_free(CrsRangeSet *range_set)
+{
+ g_ptr_array_free(range_set->io_ranges, true);
+ g_ptr_array_free(range_set->mem_ranges, true);
+}
+
static gint crs_range_compare(gconstpointer a, gconstpointer b)
{
CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
@@ -831,18 +848,17 @@ static void crs_range_merge(GPtrArray *range)
g_ptr_array_free(tmp, true);
}
-static Aml *build_crs(PCIHostState *host,
- GPtrArray *io_ranges, GPtrArray *mem_ranges)
+static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
{
Aml *crs = aml_resource_template();
- GPtrArray *host_io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
- GPtrArray *host_mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
+ CrsRangeSet temp_range_set;
CrsRangeEntry *entry;
uint8_t max_bus = pci_bus_num(host->bus);
uint8_t type;
int devfn;
int i;
+ crs_range_set_init(&temp_range_set);
for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
uint64_t range_base, range_limit;
PCIDevice *dev = host->bus->devices[devfn];
@@ -866,9 +882,11 @@ static Aml *build_crs(PCIHostState *host,
}
if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
- crs_range_insert(host_io_ranges, range_base, range_limit);
+ crs_range_insert(temp_range_set.io_ranges,
+ range_base, range_limit);
} else { /* "memory" */
- crs_range_insert(host_mem_ranges, range_base, range_limit);
+ crs_range_insert(temp_range_set.mem_ranges,
+ range_base, range_limit);
}
}
@@ -887,7 +905,8 @@ static Aml *build_crs(PCIHostState *host,
* that do not support multiple root buses
*/
if (range_base && range_base <= range_limit) {
- crs_range_insert(host_io_ranges, range_base, range_limit);
+ crs_range_insert(temp_range_set.io_ranges,
+ range_base, range_limit);
}
range_base =
@@ -900,7 +919,8 @@ static Aml *build_crs(PCIHostState *host,
* that do not support multiple root buses
*/
if (range_base && range_base <= range_limit) {
- crs_range_insert(host_mem_ranges, range_base, range_limit);
+ crs_range_insert(temp_range_set.mem_ranges,
+ range_base, range_limit);
}
range_base =
@@ -913,35 +933,36 @@ static Aml *build_crs(PCIHostState *host,
* that do not support multiple root buses
*/
if (range_base && range_base <= range_limit) {
- crs_range_insert(host_mem_ranges, range_base, range_limit);
+ crs_range_insert(temp_range_set.mem_ranges,
+ range_base, range_limit);
}
}
}
- crs_range_merge(host_io_ranges);
- for (i = 0; i < host_io_ranges->len; i++) {
- entry = g_ptr_array_index(host_io_ranges, i);
+ crs_range_merge(temp_range_set.io_ranges);
+ for (i = 0; i < temp_range_set.io_ranges->len; i++) {
+ entry = g_ptr_array_index(temp_range_set.io_ranges, i);
aml_append(crs,
aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
AML_POS_DECODE, AML_ENTIRE_RANGE,
0, entry->base, entry->limit, 0,
entry->limit - entry->base + 1));
- crs_range_insert(io_ranges, entry->base, entry->limit);
+ crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
}
- g_ptr_array_free(host_io_ranges, true);
- crs_range_merge(host_mem_ranges);
- for (i = 0; i < host_mem_ranges->len; i++) {
- entry = g_ptr_array_index(host_mem_ranges, i);
+ crs_range_merge(temp_range_set.mem_ranges);
+ for (i = 0; i < temp_range_set.mem_ranges->len; i++) {
+ entry = g_ptr_array_index(temp_range_set.mem_ranges, i);
aml_append(crs,
aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
AML_MAX_FIXED, AML_NON_CACHEABLE,
AML_READ_WRITE,
0, entry->base, entry->limit, 0,
entry->limit - entry->base + 1));
- crs_range_insert(mem_ranges, entry->base, entry->limit);
+ crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
}
- g_ptr_array_free(host_mem_ranges, true);
+
+ crs_range_set_free(&temp_range_set);
aml_append(crs,
aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
@@ -1898,8 +1919,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
{
CrsRangeEntry *entry;
Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
- GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
- GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
+ CrsRangeSet crs_range_set;
PCMachineState *pcms = PC_MACHINE(machine);
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
uint32_t nr_mem = machine->ram_slots;
@@ -1988,6 +2008,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
}
aml_append(dsdt, scope);
+ crs_range_set_init(&crs_range_set);
bus = PC_MACHINE(machine)->bus;
if (bus) {
QLIST_FOREACH(bus, &bus->child, sibling) {
@@ -2014,8 +2035,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
}
aml_append(dev, build_prt(false));
- crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent),
- io_ranges, mem_ranges);
+ crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
aml_append(dev, aml_name_decl("_CRS", crs));
aml_append(scope, dev);
aml_append(dsdt, scope);
@@ -2036,9 +2056,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
AML_POS_DECODE, AML_ENTIRE_RANGE,
0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
- crs_replace_with_free_ranges(io_ranges, 0x0D00, 0xFFFF);
- for (i = 0; i < io_ranges->len; i++) {
- entry = g_ptr_array_index(io_ranges, i);
+ crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
+ for (i = 0; i < crs_range_set.io_ranges->len; i++) {
+ entry = g_ptr_array_index(crs_range_set.io_ranges, i);
aml_append(crs,
aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
AML_POS_DECODE, AML_ENTIRE_RANGE,
@@ -2051,9 +2071,10 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
AML_CACHEABLE, AML_READ_WRITE,
0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
- crs_replace_with_free_ranges(mem_ranges, pci->w32.begin, pci->w32.end - 1);
- for (i = 0; i < mem_ranges->len; i++) {
- entry = g_ptr_array_index(mem_ranges, i);
+ crs_replace_with_free_ranges(crs_range_set.mem_ranges,
+ pci->w32.begin, pci->w32.end - 1);
+ for (i = 0; i < crs_range_set. mem_ranges->len; i++) {
+ entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
aml_append(crs,
aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
AML_NON_CACHEABLE, AML_READ_WRITE,
@@ -2088,8 +2109,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
aml_append(dev, aml_name_decl("_CRS", crs));
aml_append(scope, dev);
- g_ptr_array_free(io_ranges, true);
- g_ptr_array_free(mem_ranges, true);
+ crs_range_set_free(&crs_range_set);
/* reserve PCIHP resources */
if (pm->pcihp_io_len) {
--
2.4.3
^ permalink raw reply related [flat|nested] 9+ messages in thread* [Qemu-devel] [PATCH V4 5/6] hw/apci: handle 64-bit MMIO regions correctly
2016-06-30 19:07 [Qemu-devel] [PATCH V4 0/6] pxb: fix 64-bit MMIO allocation Marcel Apfelbaum
` (3 preceding siblings ...)
2016-06-30 19:07 ` [Qemu-devel] [PATCH V4 4/6] acpi: refactor pxb crs computation Marcel Apfelbaum
@ 2016-06-30 19:07 ` Marcel Apfelbaum
2016-06-30 19:07 ` [Qemu-devel] [PATCH V4 6/6] tests/acpi: Add pxb/pxb-pcie tests blobs Marcel Apfelbaum
2016-07-01 13:57 ` [Qemu-devel] [PATCH V4 0/6] pxb: fix 64-bit MMIO allocation Laszlo Ersek
6 siblings, 0 replies; 9+ messages in thread
From: Marcel Apfelbaum @ 2016-06-30 19:07 UTC (permalink / raw)
To: qemu-devel; +Cc: marcel, mst, pbonzini, imammedo, lersek, ehabkost
In build_crs(), the calculation and merging of the ranges already happens
in 64-bit, but the entry boundaries are silently truncated to 32-bit in the
call to aml_dword_memory(). Fix it by handling the 64-bit MMIO ranges separately.
This fixes 64-bit BARs behind PXBs.
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
---
hw/i386/acpi-build.c | 53 +++++++++++++++++++++++++++++++++++++++++++---------
1 file changed, 44 insertions(+), 9 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index eca195d..cfcca71 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -750,18 +750,22 @@ static void crs_range_free(gpointer data)
typedef struct CrsRangeSet {
GPtrArray *io_ranges;
GPtrArray *mem_ranges;
+ GPtrArray *mem_64bit_ranges;
} CrsRangeSet;
static void crs_range_set_init(CrsRangeSet *range_set)
{
range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
+ range_set->mem_64bit_ranges =
+ g_ptr_array_new_with_free_func(crs_range_free);
}
static void crs_range_set_free(CrsRangeSet *range_set)
{
g_ptr_array_free(range_set->io_ranges, true);
g_ptr_array_free(range_set->mem_ranges, true);
+ g_ptr_array_free(range_set->mem_64bit_ranges, true);
}
static gint crs_range_compare(gconstpointer a, gconstpointer b)
@@ -919,8 +923,14 @@ static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
* that do not support multiple root buses
*/
if (range_base && range_base <= range_limit) {
- crs_range_insert(temp_range_set.mem_ranges,
- range_base, range_limit);
+ uint64_t length = range_limit - range_base + 1;
+ if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
+ crs_range_insert(temp_range_set.mem_ranges,
+ range_base, range_limit);
+ } else {
+ crs_range_insert(temp_range_set.mem_64bit_ranges,
+ range_base, range_limit);
+ }
}
range_base =
@@ -933,8 +943,14 @@ static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
* that do not support multiple root buses
*/
if (range_base && range_base <= range_limit) {
- crs_range_insert(temp_range_set.mem_ranges,
- range_base, range_limit);
+ uint64_t length = range_limit - range_base + 1;
+ if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
+ crs_range_insert(temp_range_set.mem_ranges,
+ range_base, range_limit);
+ } else {
+ crs_range_insert(temp_range_set.mem_64bit_ranges,
+ range_base, range_limit);
+ }
}
}
}
@@ -962,6 +978,19 @@ static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
}
+ crs_range_merge(temp_range_set.mem_64bit_ranges);
+ for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) {
+ entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i);
+ aml_append(crs,
+ aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
+ AML_MAX_FIXED, AML_NON_CACHEABLE,
+ AML_READ_WRITE,
+ 0, entry->base, entry->limit, 0,
+ entry->limit - entry->base + 1));
+ crs_range_insert(range_set->mem_64bit_ranges,
+ entry->base, entry->limit);
+ }
+
crs_range_set_free(&temp_range_set);
aml_append(crs,
@@ -2083,11 +2112,17 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
}
if (pci->w64.begin) {
- aml_append(crs,
- aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
- AML_CACHEABLE, AML_READ_WRITE,
- 0, pci->w64.begin, pci->w64.end - 1, 0,
- pci->w64.end - pci->w64.begin));
+ crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
+ pci->w64.begin, pci->w64.end - 1);
+ for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
+ entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
+ aml_append(crs,
+ aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
+ AML_MAX_FIXED,
+ AML_CACHEABLE, AML_READ_WRITE,
+ 0, entry->base, entry->limit,
+ 0, entry->limit - entry->base + 1));
+ }
}
if (misc->tpm_version != TPM_VERSION_UNSPEC) {
--
2.4.3
^ permalink raw reply related [flat|nested] 9+ messages in thread* [Qemu-devel] [PATCH V4 6/6] tests/acpi: Add pxb/pxb-pcie tests blobs
2016-06-30 19:07 [Qemu-devel] [PATCH V4 0/6] pxb: fix 64-bit MMIO allocation Marcel Apfelbaum
` (4 preceding siblings ...)
2016-06-30 19:07 ` [Qemu-devel] [PATCH V4 5/6] hw/apci: handle 64-bit MMIO regions correctly Marcel Apfelbaum
@ 2016-06-30 19:07 ` Marcel Apfelbaum
2016-07-01 13:57 ` [Qemu-devel] [PATCH V4 0/6] pxb: fix 64-bit MMIO allocation Laszlo Ersek
6 siblings, 0 replies; 9+ messages in thread
From: Marcel Apfelbaum @ 2016-06-30 19:07 UTC (permalink / raw)
To: qemu-devel; +Cc: marcel, mst, pbonzini, imammedo, lersek, ehabkost
Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
---
tests/acpi-test-data/pc/DSDT.pxb | Bin 0 -> 6280 bytes
tests/acpi-test-data/q35/DSDT.pxb_pcie | Bin 0 -> 9098 bytes
2 files changed, 0 insertions(+), 0 deletions(-)
create mode 100644 tests/acpi-test-data/pc/DSDT.pxb
create mode 100644 tests/acpi-test-data/q35/DSDT.pxb_pcie
diff --git a/tests/acpi-test-data/pc/DSDT.pxb b/tests/acpi-test-data/pc/DSDT.pxb
new file mode 100644
index 0000000000000000000000000000000000000000..1733aeceb843c449d7560d4728115b096e709da2
GIT binary patch
literal 6280
zcmb_gZEqXL5uW9XbX-!>Q98@=TTIAy+@!J17e{u`q7ZpUiL`jsnMb*9Pv{+G8KsN_
zJ}5RC#Rx(%fTH+Yz`AHZl{WO*`U(9D`3dP?NYU7ztj^qVDVov&4p0K3c4nTPm))7!
zU23LQ-<<(qnZmMKGE;@ShN>Zt0RWBZzg&*2g4NOri#CggBFx&3dt>}6NXkcAVP%p1
zz3KeTaUOl^u!ak3FXU%y4fmT}XAKDSc+KUU2J)<J7Hq41#!$;?$u5<(ME(aJmh8M%
z1Ib<~YfRQ9A5)Y{MzJnH3_&PHH%dlbhXlY6Z{iTKwq>HH?i8z9%BX2}N}03GdLCTj
zI4-doUpicNx{2>Q4s@LO!NDGM$G`71;IEAY{QJMrJ=o(DlC9RvWRj2X#4uu14iSJY
zkS|>&Z^&J%eag6-$$7pe!obiKBa>4@zz^j4=m1QOl+C>D<8WaKcRj6!xWm!i_y2U2
zw9rg|(lr>Z7{w}sn-Es>GzhB&{3omDuZ4wS(q^@<)aoiK^_MJ;i$(s<@Dq#71sCMd
zEU-nk37Zfa*#fJ5W2vC^;o-0n^H!xFs5j982N=#;hjsiv8^U<4_GNu}r9W|EYIvf=
zqq86rFfT1=YJU?)dmf$PGmGq}@K0fgEV5VOSGZ8K^YCHB)16tU7<sYT3tD+HB?FK0
zWu9hypNIG*{F~%w_yPZv|I8=2B-smEF?o_Jl!k+!5E54VcNL@F_ca2_jKB4?q)vAP
zw|ftsNBS|#d~A_@5&j}9NwY1_pJGH^)-z&Jqs-4hp@udjNX_f;>o7>OvZrQ&)MSU$
z@K9e5?r5N%(CZNDkx-9Zk`9xoWvFJI#o;BFFvW>bF$Y&t_@$++mRY=or6|3mjEWPX
z7ShFAC@56*8jH)mfC#lvUC~n(D^%1aP%as2@m9#XK-9s3+a#g8#WsMZTbGHw2XYll
zs9?)WoYG#=xNX$x;7*2Gjth+!h1jzOZ@FJKcnH?qC!38m;9<Del{@zk6vMKqRF^bZ
z?_TWOW8Gw@!6SXP3G2_t`cxi4$<93<>T?P`PPoreVcq>|YmLi*g$uju0Pd3p+S^@c
z;I8jF4S3wxbFA%)*TUp2)e2P`GitZf5`JaqD@$KFNtr6&##Qacp72%^i$1o;<H}t5
zwpxoJpq5UK^Z0io5c8643!V~>NAbJdjX!H*%uO2a5!-54MlnoGX1^d4*g&W~Nw`*K
za+*(lHx99I6tk4$UmX9oK$-Askend*l%%bdP56q&yybBwsH$O)T=M9XwplaT)28nQ
zcC%WU_&w`|A?ujG?`%CYU_Ikm&!B&U)-%fS)-zUHr`XjY>pb)e%x4G8XFc=TA@kV)
z^VyzxZP+{>5bqp)ZoqubGoKqWp9?Ubv)aoMjNTkJAMwqL6rxiEw_LQ{xH95xwi5T(
zm|R5`?XFzD;U9P^Up;L4My=R4!AHF08dHsxRO#U(_tVFJPHo=*{Ndxxd-p#Fi>XFs
zsn>qTIA3J25Bn^EJsOkB>mvI+VQpU^A`dB*4ji>yHJMt|?=Wl#X$BEh)irE2lLQK@
zX0eh&q?WIzl!RTbmL(U6iHY~os@J8^7vI0JylRxw=}ekD@Xzz8l2q#pe+YGXrwKc1
zI-TB7N+a0A@-gee>a~bC*eFKwojTDl8;!Z(bWeAN1?0WUCmieY5lLlf&r$R!MfA%I
zv0+uH;aL4jX<RkcsuUCkb6(`*9S4tOY?Z@GafQ2!ks|?lJAunJ49CT1?h(%r?K0>2
zQlwits><8X<5ltSQC$c}UB?Hi$JAxBo(Kx`*!?=<EJo~Z921wzL&IExJ{V@=5*+KD
z^$nifm{wS0_`wXt)ROin!7vH+d_5WG5=eCSLTTKl45y?3W!%P~;uIM)Hy$WwFqapN
zqFqd9aksn+7v(i=v0S}!cpA6!SM-wMcbqY!YNYe&Ikbcge@wss*~87PRP#t#DpOv!
z@5Va1R;}Sp1P>dF>E1D%AJNeS9Lg|XtP3PNIC$~fXAaG99UW_+JJr!CL3G?zOe;pj
z^XabA(P^(eF6}H)n-1+IDcNJn6`d-7K&|_aCU^?t9ldDUy%O@!j*_3zvGZfi_$~;n
zq}S%ICv!ag^w$7*<sJIGIq*M%-6Ie1<fMsw9G$KB!$};L{NekRqTqgr!yb29&)@A~
zPvfxU>a{|NCeffmif~XV(F7V)NXaI#X+U#{@WeE`t2`qf$v25+9y94N*`q#(Mir7(
zy4q-m*nlDDvdQ!O?6)TeL#9wEObXEpFPG&U)!P^o4##nBZ#az(*)CZou}jKH=#rl#
z>g^Cs>ksFyD;IU+uFi%xz(uYtHq}vnrDNhoj(|4w<>DRp0SZ-Lr828yw&OML?d`-g
z!JDEFk;@~L`Q9Pc>)@Eu$|qO~8K9!?zdrn{;sC=?t6o*Ug-}l6%-mqhqk^F<mn+HD
z-uad^)SLKVz_Q^jaeUI_uTZG+mNFm1Lvi4qSsi`HdnR5yS^vKH|GQKAFRW^m|Iy2Z
z-V3CKsqoJ?e#)o7D~z|^CPYw{yv0Nw(Ys?1!iOugU>m>bxg{@8`o}5VU44TUiSG&^
zz}Fspk-bj5PB01i%&)^&sONQ}Pmg)&`Jch0<>&_8JLwaG!4N<?IQY63LhI*2Nf(3r
zS3fv<<f#$N6917m)cA-$a0|gldp*zNehl6%<j4IV_gRFL+=>__qvq$@+uakxKITSq
zR2RI2mrTL+`d}6Nu9>qZM<NWD6vx-?NhyNwMtl(>^)X2(WcfFT3v0EnF8p3y@Ey2a
z)K~E6$P#+UV>v2E>E0x(fALZle~K8$d+!ABdig+*c)jN^LszYmK`$@he8$>7PehnH
zSBm-=epP5x!4Vd8%Gy3hfIQ4|uNPydzz**<bb8lW+b8__bPJ=}#xGM%DI?VGL-N9B
zUa}NWifbD;(`kGH)9)u%`$IF+BQQNepkRm@4UZlgWW^vy1FJn@W^Vcu5gSIv2WFNg
zn=4h0cUe@3e0)<+ddDZd8_6PxJt)m3XjDL>LC~Dginmx_>qsC}XdM;M(IDt`p%s54
z@U=>TP@y#@ps^t6$3iO?P#y>sS~2H+2jW4{IiWQnpou`J&^jidV?odxLhHDIjt4@8
zR(z%UzD@)|ZwjrlfXabTp*1O>$sp(_LhGb}P6k4S)+qs<3WDZ^R?KfdEF};sw4M;q
z6G6~|&^j%k(}7T-^`wBF41%gc>x_WT1VV+@Qv!M_2&xIKrv>zMAXI2QBcNx3phcne
ztbm>kgbJ<a1oT`GbU|o+Pe9)bgbJ<a1@!!JP-W?~cBfhobrVmT_yf@nHLwkjND*<f
zN6aIEO~{wDh#<+>lV%)G<sB0{NskH<)t5z(!hX<`NksK!WDKjiCnIZfeHod<+U&{5
z-VKsXJZWM>#WQQi#2OPco?1vB%JJ;lF|k^N93L@AAIfE-G4F*u<<W=od7?3cg}mj_
zhjK4s%tax`Q)0(d2jmnrW>sHKaccu|iX8K!FHaFYAfHDXce*cc5sh-?Jlz}dmumXS
Pk#-Fau@%-EXgvHs$6*Lt
literal 0
HcmV?d00001
diff --git a/tests/acpi-test-data/q35/DSDT.pxb_pcie b/tests/acpi-test-data/q35/DSDT.pxb_pcie
new file mode 100644
index 0000000000000000000000000000000000000000..838ca876dece056934ed511197c2a8fa0d27fd11
GIT binary patch
literal 9098
zcmb7KU2hx56`dt1YB{8&rL>aeuZXaVrb*+3l3XX~M__W7B3W@Iilp;V8XzSrt(>&T
zLa~83Mi5B>62}h(62?LMRNByU{zCH;^40)->SOy_6!BBkb7yww8BzjbJ}l?Xo^$V<
z-Pt+IUHVPGb^jt`*1wDEUZt5UzESsl^jVBCYSXt<O<ZT~J-=A)Sm{{8YVW5-8=Io-
zzTg+Hm94+*bie9$Z++UeHbb`c$a%1}8Gd}PyTu4}dn@Fe8qRZ_X0g-Wt9#9sm1bY_
zjA$3FbmnVHi~i!(x>qgQ&U!{b56T(DdAn1o`kBJF+_pQOY{l(P!EZ3TbFJ!IcJo@j
z&TOyMs4>@1b=I3+;{H3#^Iu==uZ;J0vNPOi2mf6De&O8JuU@}Z_~tkN`2GENcmjYW
zeB1b54k@5K)L5oecWJ}V)3)z?(YtAVh&_t}z1W}oqNi}O+o7EyfvNvtM)p#P#lv@;
zz?OPScBNiwDLoccVEj0`m3k{+8OFZ-A<Yu)eTU+i*Gg-CuHNuFIrmDZ*($J*db%NX
zZGO<@PPd==yw_#DZu;oxko6}&?`^U#H#6*C{~J4GhkOc0tI^D6`Q#@loJb^R3C8X)
z=j!;2G#om#?E^1aZ5BG>aAE)p7)-s|*og5iot_%zLyYh7SbP68wVAgb6ynUnR}o*e
zddrUqR4K*}2sH~-iFt+6n&lO-snxM@uAX`+t}0Ts_Q9n_%R^ClUeh>_G}3uKTed<L
zGADL{S!HXN?Xp<%4r?F0yjt`J@Oa!!iQ_SlD2QFwWfoZ5Y#ZMfVo=&Xcs5wSHXu&T
z3=?fWc7Ztrd=**-zyx#W<q@axcl${k<wN!`F(~NpiL&*6{QbCXU)U3cN(mg3MWtxW
zk~34Kp#ySKn#b|Sab{m|M4A;!vow^3#|C+DOi#=cdmKX^8+q({)mve1rh{)Q+@Z+%
z^P3i(0>}H0xTNZhR(*Q)y}jvl0<(wJ)>cbQwk@<**mQ>ac?>~W1#tuwHa(HZ935e4
zkhmx!7J!p-pWp$iLSiDnz{Ug<*eD{Vg2tF&0xFmYiHXq&Y+Nwa2x$I^tO6RBOh8pg
zOjQN*USdU_gkUOYLNe9h5$Za}44q?wsi0$$sRoZw*O@eQCIwSLlcr9Dy3TP!=eVJB
z+|-Fs*J&F%Z9}JR>O`pP#0sGu>6D=}W$Hwz>*R(`Zs_EuPK3J7w4pO?=uDeB5$Zaz
zQfcQiW9ZD7IuYtRCk&kvhRz97CqiB4q@i=t&^c-9M5ybWGIUNEI;TvX2z8x~q0=#R
zI;Kv9y3VYjGi&I~nmQ5cI;Rbt(}vDzQzt@Q=Zv9q#?U!q>O`pPbPb)Zq0=>WBGh%x
z8aihUowKG+gu2c-L+6~KbI#O>P}h0N(0R(xdCJs@P}ezc=$ton&YL<B>N-ygW+7S$
zPYY%-TI^0sruQTyrXOL?7|b&U^Nh(vs58$R%(DjbtjR>EGtU{!a|ZLA$wa6#&l}A1
z2J^hhM5r^L5lrPW&j_Yk<DZdCwQwUOrgD-6qvnE9bHS{MP}a0zpaso9%gyS*K+#6w
z$UqUGtPJ7^R8bhH#0g8XaK9sf$}wXSszPEaX)sWURR*d-$v`DkFv&m>Vl>J?B{qtv
zrt(@cPzfCvC_)TfU}2yV8%4xa2bT;~LIsly6rs`y1C?08gn?>MGEfN>Ofpb}N+%3d
zVg(ZhszJ#>B~&oUKoKgPFi?pVOc<yJB?FaE!6XAksC2?WB~~zDpc<46R6+%l3>2Z#
z2?Lc_!GwWoP%=;n6-+Wvgi0q2RAL1a2C6~HKqXW#$v_b*oiI>|6-*eY1|<WPP{AYv
zMW}SbKqXc%VW1k63{*k|lMEE0(g_2VSiyvWYEUvz2^CB-P=rb+3{+wT69%e5$v`Dk
zFv&m>DxEM;i4{y3s0Jkil~BPX14XEG!ayZfFkzq?lnhit1(OUEq0$Khl~}=qfof1P
zPze=GGEjs{Ck#|#1rr9ULCHWRR4~av5h|T9P>B^x7^ns%1C>z0Bm+gLbizO-Rxn|p
z8k7uFLIsly6rs`y1C?08gn?>MGEfN>Ofpb}N+%3dVg(ZhszJ#>B~&oUKoKgPFi?pV
zOc<yJB?FaE!6XAksC2?WB~~zDpc<46R6+%l3>2Z#2?Ir>87Ly%KoRN&icm99jR^zQ
zm}H<DlMGa2!ay}93{+#1foe=LP>l%#)tE3)jY$ToG08wRCJa<#!ay}98K}l21J#%?
zP(<qN!axz>jERFu28s};L50Lr#})>PNF7@kC?a)i$v_dRV@n2#&}Z(M4lI=QGd=NR
z^^ks$K1|YAp}qghm*Vs*m7W#Q(+I2H*eJkpH;T0JXye-q&qg*%)Lx-YnKl*MovCi%
z@lro^m+$T1AxP?wr`^ld4X=>`ppnl`^7Lm(mZC>n_@#WG`uG^O)$r~PpJLR)AR2fw
zQX9uTLP7l&&){(iJ*=@Y>}Gb3&wMt?QgOH&!}`sz5+j>CC7(;s5HOm8o9+13Ci{@u
zd{6XD(UT5#NCOh_sZO)ewC?XjW1#ZXA5||7RmWq6A6>nuRWFL_MT}3cUUZMIUThx(
zq}>~;&SOte-qXr^qP#a$-aDbZ7nS#i%j0p`k5=z%<$Y1!A1d#kP~MNqmxjwHo}zq7
zD_;`jOGD*LCzLNm<yVHwk3B{C6|MY=D8DjPe&vMnD^dCKaQWm@lrL-L%c6XFsC@Z^
z^5v*}Ww`wKQ<Sf0<tw6mWvG1Rgz^=XPtZ~}T;7r8)#8EM3VO^Yo?4oHZc<$G_@e7N
zN;iBN^Q@T;_ZlPVWZ$vrMy|_gGaYU~M$*Z?W7CaXXESCx+?9-^lYPgg8@X;=GaYVK
zM$*Z?W7CaX2eW26+`o*ZlYPgg8=2R0W;)!|jHHu&$EF*Zr>D$xxYHR)C;QBFPW5H^
zhQQ<3pFAtCH%d)46FDwG_|Jq_zm}`Kdn^3o?LXvp-+J%e+q*a3dXKd&uU=b?X5<9t
zW$U}lcNr^#N89indf)P01`qW2FH%roIgg&pd)2k3<u!uWEU)z2yu}ip7x;F2f0{sX
zuUV?)fb<Kk93CZC*Q$2Ns1x4w!gcWm0b`Nln<#koYCgZ1rxD0EG-GboYpuK)>+{|Y
z`^3xV^Ecf}60d#=srJR|FD2Cb0MbZfKROC`hPzQLWZnLm-tZ0@eaNS}?Po{!)K(9>
zZZJlQp01EJoC+C^&F@wwy{5NjpCrTTJ}RVpUA)QYhHN+~j&Q%67!f4S1P<3Q90%VD
zM@9y8Xmua1Ci<1pRN{OdpNhvva{-QA#|sTo-g>i@IZ5cT=WArJP#oSoMpwvV!@UH3
zd$<#a;Mmc%KgK&3Oe<Vr_+W-&YT1W0!7vGfLMxl*HpB0Ey3=#h9h%`ZDVRHn7lf@e
zDPub~-*(SpE|=@2PAR{HvnAeB(Y&Tp?5thV-jo$C1(mv7EGOz~^?V_J1(oQU4Bq<F
zySsOCJ0q8+J0org`>9^wuQl)v33sDyE2w#^%q=7XlweQxVZO94(!QgkN56j1B}Ui{
za1HcldI3$40B04`%A(-mT;J^lbgo4&omq-@yL2uo$)V+53h2t$(uRNCVIpC=7nGWv
z=n@j>u3MN7aC3-jMh-z??Vxexa(0>L@Bf^!3|_&QpC69oNA*VG5pJ!C$R{z_nru#^
zS&_}3)=H}Pc{HQmxuEbyggt|1B@7zH3X!N$qeN)bDny`0jgstAH#LY$f!Iy#zWads
zX#Xz7mgvliPV3g7hgvn-SL^%ZJ?dtVyu6fM;O9QYQvF0SNhO&iQOH|f;vDHa(1hkB
zxKVQs1L}lSnRbVioOXsZPTCcnA)*bMS1!9h3F>bI*6;}k(c4icwd?*Yz{E|AfNlos
zrPso@vD1?&-3tL`du#+~p*tFYBPPBum}mjVjCN1sN?6v{Et>T-Rh?S)dSp`By7vlR
z%VX~Iy@5gD_PkhJ<9qJal=x{EPRI7J0&YH98-K9L_rec0d5mp^cXv0p@FS4j=sUd|
zESyfsmvcVbrVeY+Q9wtwcZ0_UJ;kUeKIrk-cKG3)E$%RSiFt3EvGDFDa^KswSh#(!
zyUA{E9(Lt@+S(ZZoj9T5rypZ`IG=y}LC)J86SF(oBl{?zQ*CsjkK%h1EQUvDY>(|@
zORt(8Z&G@q{KEph&aT<~o&qxVk${)2$C<|&%SOK?XV&+~^EfkzC&V24uRilQhC#nC
z=@VnR1oq9*(MOSly;t=;eTe(}Kpef`_7Yg+<X<U<Rxj$;ZYA(ng;s&5<v|m-61ik9
zY2huo^W1eTc+KU`bTVP#Fra<8Gi@h$3@4VNU(g;Jrt_;O2cv!P;>zouyp5aKC<WKB
zW-k$XsERY@jL{8?<4=ichCfYcw?bm+6^p1gF#Po9Y@Y6MD)pd&|CDe(-`-!KAWln0
zjusGXYSgNsg)1r7-ak)(0=vq^B8W>AORHE(ab@6-D6^7Jw?A}IVbk<-Zj#p7m{T5;
zf15}*^LhMVfc}KiK6t*Fe?<m3nHIwhZ*$SdYEO+N)mWxR`(UcM7!iSuF*jNF)>`cU
D-{y{a
literal 0
HcmV?d00001
--
2.4.3
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [PATCH V4 0/6] pxb: fix 64-bit MMIO allocation
2016-06-30 19:07 [Qemu-devel] [PATCH V4 0/6] pxb: fix 64-bit MMIO allocation Marcel Apfelbaum
` (5 preceding siblings ...)
2016-06-30 19:07 ` [Qemu-devel] [PATCH V4 6/6] tests/acpi: Add pxb/pxb-pcie tests blobs Marcel Apfelbaum
@ 2016-07-01 13:57 ` Laszlo Ersek
2016-07-01 14:15 ` Marcel Apfelbaum
6 siblings, 1 reply; 9+ messages in thread
From: Laszlo Ersek @ 2016-07-01 13:57 UTC (permalink / raw)
To: Marcel Apfelbaum, qemu-devel; +Cc: ehabkost, mst, imammedo, pbonzini
On 06/30/16 21:07, Marcel Apfelbaum wrote:
> 64-bit BARs allocations fix for devices behind PXBs/PXB-PCIEs.
>
> In build_crs() the calculation and merging of the ranges already happens
> in 64-bit, but the entry boundaries are silently truncated to 32-bit in the
> call to aml_dword_memory(). Fix it by handling the 64-bit MMIO ranges separately.
>
> v3 -> v4:
> Addressed Igor's comments (thanks for the productive review!)
> - Split pxb test patch (previously patch 3/3) into the test itself (patch 1/6) and the blobs (patch 6/6).
> - New patch declaring pxb/pxb-pxie as not hot-pluggable.
> - Note that it does not solve the DSDT issue, but it is a prerequisite for the next patch.
> - New patch solving the DSDT issue spotted by Igor.
> - Using V=1 DIFF=diff make check does make it easier to review the ACPI changes, thanks.
> - Patches 4 and 5 untouched (previously patches 1/3 and 2/3)
>
> v2 -> v3:
> - split original series "pci: better support for 64-bit MMIO allocation" into 2 series:
> - this is the first part dealing with correct 64-bit MMIO ACPI computation
> - the second one will include 64-bit MMIO reservation for PCI hotplug
> - Add pxb/pxb-pcie tests (Igor) - See diffs below (*)
> - Re-based on latest master.
>
> v1 -> v2:
> - resolved some styling issues (Laszlo)
> - rebase on latest master (Laszlo)
>
> Thank you,
> Marcel
>
> Marcel Apfelbaum (6):
> tests/acpi: add pxb/pxb-pcie tests
> hw/pxb: declare pxb devices as not hot-pluggable
> hw/acpi: fix a DSDT table issue when a pxb is present.
> acpi: refactor pxb crs computation
> hw/apci: handle 64-bit MMIO regions correctly
> tests/acpi: Add pxb/pxb-pcie tests blobs
>
> hw/i386/acpi-build.c | 131 ++++++++++++++++++++++++---------
> hw/pci-bridge/pci_expander_bridge.c | 2 +
> tests/acpi-test-data/pc/DSDT.pxb | Bin 0 -> 6280 bytes
> tests/acpi-test-data/q35/DSDT.pxb_pcie | Bin 0 -> 9098 bytes
> tests/bios-tables-test.c | 37 ++++++++++
> 5 files changed, 134 insertions(+), 36 deletions(-)
> create mode 100644 tests/acpi-test-data/pc/DSDT.pxb
> create mode 100644 tests/acpi-test-data/q35/DSDT.pxb_pcie
>
I used the following commands to test (part of) the series:
> VIRTIO10=1
> ISO=/mnt/data/isos/iso-fedora/Fedora-Workstation-Live-x86_64-24-1.2.iso
> CODE=/home/virt-images/OVMF_CODE.fd
> TMPL=/home/virt-images/OVMF_VARS.fd
> TFTP=/var/lib/dnsmasq
> BF=shim.efi
>
> if [ $VIRTIO10 -eq 0 ]; then
> MODERN=disable-legacy=off,disable-modern=on
> else
> MODERN=disable-legacy=on,disable-modern=off
> fi
>
> cp $TMPL vars3.fd
>
> qemu-system-x86_64 \
> -m 2048 \
> -M pc \
> -enable-kvm \
> -device qxl-vga \
> -drive if=pflash,readonly,format=raw,file=$CODE \
> -drive if=pflash,format=raw,file=vars3.fd \
> -drive id=cdrom,if=none,readonly,format=raw,cache=writethrough,file=$ISO \
> \
> -debugcon file:debug3.log \
> -global isa-debugcon.iobase=0x402 \
> \
> -chardev stdio,signal=off,mux=on,id=char0 \
> -mon chardev=char0,mode=readline,default \
> -serial chardev:char0 \
> \
> -device pxb,bus=pci.0,id=bridge1,bus_nr=11 \
> -device pxb,bus=pci.0,id=bridge2,bus_nr=7 \
> -device pxb,bus=pci.0,id=bridge3,bus_nr=15 \
> \
> -device virtio-scsi-pci,id=scsi0,$MODERN,bus=pci.0 \
> -device scsi-cd,bus=scsi0.0,drive=cdrom,bootindex=1 \
> \
> -netdev user,id=netdev0,hostfwd=tcp:127.0.0.1:2227-:22,tftp=$TFTP,bootfile=$BF,net=10.0.2.0/24 \
> -device virtio-net-pci,netdev=netdev0,romfile=,$MODERN,bootindex=2,bus=bridge1,addr=2 \
> \
> -netdev user,id=netdev1,hostfwd=tcp:127.0.0.1:2228-:22,net=10.0.3.0/24 \
> -device virtio-net-pci,netdev=netdev1,romfile=,$MODERN,bootindex=3,bus=bridge2,addr=3 \
> \
> -netdev user,id=netdev2,hostfwd=tcp:127.0.0.1:2229-:22,net=10.0.4.0/24 \
> -device virtio-net-pci,netdev=netdev2,romfile=,$MODERN,bootindex=4,bus=bridge3,addr=4 \
> \
> -global PIIX4_PM.disable_s3=0 \
>
This is /proc/iomem from within the guest:
> 00000000-00000fff : reserved
> 00001000-0009ffff : System RAM
> 000a0000-000bffff : PCI Bus 0000:00
> 000f0000-000fffff : System ROM
> 00100000-007fffff : System RAM
> 00800000-00807fff : ACPI Non-volatile Storage
> 00808000-0080ffff : System RAM
> 00810000-008fffff : ACPI Non-volatile Storage
> 00900000-7e529017 : System RAM
> 02000000-027d3cf3 : Kernel code
> 027d3cf4-02d4dfff : Kernel data
> 02edc000-0305dfff : Kernel bss
> 7e529018-7e532857 : System RAM
> 7e532858-7e800fff : System RAM
> 7e801000-7e820fff : ACPI Non-volatile Storage
> 7e821000-7e84afff : reserved
> 7e84b000-7ebe1fff : System RAM
> 7ebe2000-7ebfdfff : reserved
> 7ebfe000-7ec22fff : System RAM
> 7ec23000-7ec35fff : reserved
> 7ec36000-7ec99fff : System RAM
> 7ec9a000-7ee16fff : reserved
> 7ee17000-7fe96fff : System RAM
> 7fe97000-7feeefff : reserved
> 7feef000-7fef6fff : ACPI Tables
> 7fef7000-7fefafff : ACPI Non-volatile Storage
> 7fefb000-7ffcffff : System RAM
> 7ffd0000-7ffeffff : reserved
> 7fff0000-7fffffff : System RAM
> 80000000-880fffff : PCI Bus 0000:00
> 80000000-83ffffff : 0000:00:02.0
> 84000000-87ffffff : 0000:00:02.0
> 88000000-88001fff : 0000:00:02.0
> 88002000-88002fff : 0000:00:06.0
> 88010000-8801ffff : 0000:00:02.0
> 88100000-881fffff : PCI Bus 0000:07
> 88100000-881fffff : PCI Bus 0000:08
> 88100000-88100fff : 0000:08:03.0
> 88200000-882fffff : PCI Bus 0000:0b
> 88200000-882fffff : PCI Bus 0000:0c
> 88200000-88200fff : 0000:0c:02.0
> 88300000-883fffff : PCI Bus 0000:0f
> 88300000-883fffff : PCI Bus 0000:10
> 88300000-88300fff : 0000:10:04.0
> 88400000-febfffff : PCI Bus 0000:00
> fec00000-fec003ff : IOAPIC 0
> fed00000-fed003ff : HPET 0
> fed00000-fed003ff : PNP0103:00
> fee00000-fee00fff : Local APIC
> ffe00000-ffffffff : reserved
> 800000000-8007fffff : PCI Bus 0000:00
> 800000000-8007fffff : 0000:00:06.0
> 800000000-8007fffff : virtio-pci-modern
> 800800000-800ffffff : PCI Bus 0000:07
> 800800000-800ffffff : PCI Bus 0000:08
> 800800000-800ffffff : 0000:08:03.0
> 800800000-800ffffff : virtio-pci-modern
> 801000000-8017fffff : PCI Bus 0000:0b
> 801000000-8017fffff : PCI Bus 0000:0c
> 801000000-8017fffff : 0000:0c:02.0
> 801000000-8017fffff : virtio-pci-modern
> 801800000-801ffffff : PCI Bus 0000:0f
> 801800000-801ffffff : PCI Bus 0000:10
> 801800000-801ffffff : 0000:10:04.0
> 801800000-801ffffff : virtio-pci-modern
It looks good to me. I also checked the _CRS objects in the DSDT in the guest (cursorily), it seemed okay.
Guest dmesg contains no problems.
The virtio-scsi CD obviously worked (booted Fedora 24 Live off of it). I also logged into the guest through all three NICs, with ssh.
Below an excerpt from the OVMF debug log -- it appears consistent with the guest's /proc/iomem:
> PciHostBridgeGetRootBridges: 3 extra root buses reported by QEMU
> InitRootBridge: populated root bus 0, with room for 6 subordinate bus(es)
> InitRootBridge: populated root bus 7, with room for 3 subordinate bus(es)
> InitRootBridge: populated root bus 11, with room for 3 subordinate bus(es)
> InitRootBridge: populated root bus 15, with room for 240 subordinate bus(es)
> RootBridge: PciRoot(0x0)
> Support/Attr: 70069 / 70069
> DmaAbove4G: No
> NoExtConfSpace: Yes
> AllocAttr: 3 (CombineMemPMem Mem64Decode)
> Bus: 0 - 6
> Io: C000 - FFFF
> Mem: 80000000 - FBFFFFFF
> MemAbove4G: 800000000 - FFFFFFFFF
> PMem: FFFFFFFFFFFFFFFF - 0
> PMemAbove4G: FFFFFFFFFFFFFFFF - 0
> PciHostBridgeDxe: IntersectMemoryDescriptor: add [800000000, 1000000000): Success
> RootBridge: PciRoot(0x7)
> Support/Attr: 70069 / 70069
> DmaAbove4G: No
> NoExtConfSpace: Yes
> AllocAttr: 3 (CombineMemPMem Mem64Decode)
> Bus: 7 - A
> Io: C000 - FFFF
> Mem: 80000000 - FBFFFFFF
> MemAbove4G: 800000000 - FFFFFFFFF
> PMem: FFFFFFFFFFFFFFFF - 0
> PMemAbove4G: FFFFFFFFFFFFFFFF - 0
> RootBridge: PciRoot(0xB)
> Support/Attr: 70069 / 70069
> DmaAbove4G: No
> NoExtConfSpace: Yes
> AllocAttr: 3 (CombineMemPMem Mem64Decode)
> Bus: B - E
> Io: C000 - FFFF
> Mem: 80000000 - FBFFFFFF
> MemAbove4G: 800000000 - FFFFFFFFF
> PMem: FFFFFFFFFFFFFFFF - 0
> PMemAbove4G: FFFFFFFFFFFFFFFF - 0
> RootBridge: PciRoot(0xF)
> Support/Attr: 70069 / 70069
> DmaAbove4G: No
> NoExtConfSpace: Yes
> AllocAttr: 3 (CombineMemPMem Mem64Decode)
> Bus: F - FF
> Io: C000 - FFFF
> Mem: 80000000 - FBFFFFFF
> MemAbove4G: 800000000 - FFFFFFFFF
> PMem: FFFFFFFFFFFFFFFF - 0
> PMemAbove4G: FFFFFFFFFFFFFFFF - 0
>
> [...]
>
> PCI Bus First Scanning
> PciBus: Discovered PCI @ [00|00|00]
>
> PciBus: Discovered PCI @ [00|01|00]
>
> PciBus: Discovered PCI @ [00|01|01]
> BAR[4]: Type = Io32; Alignment = 0xF; Length = 0x10; Offset = 0x20
>
> PciBus: Discovered PCI @ [00|01|03]
>
> PciBus: Discovered PCI @ [00|02|00]
> BAR[0]: Type = Mem32; Alignment = 0x3FFFFFF; Length = 0x4000000; Offset = 0x10
> BAR[1]: Type = Mem32; Alignment = 0x3FFFFFF; Length = 0x4000000; Offset = 0x14
> BAR[2]: Type = Mem32; Alignment = 0x1FFF; Length = 0x2000; Offset = 0x18
> BAR[3]: Type = Io32; Alignment = 0x1F; Length = 0x20; Offset = 0x1C
>
> PciBus: Discovered PCI @ [00|03|00]
>
> PciBus: Discovered PCI @ [00|04|00]
>
> PciBus: Discovered PCI @ [00|05|00]
>
> PciBus: Discovered PCI @ [00|06|00]
> BAR[1]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x14
> BAR[4]: Type = PMem64; Alignment = 0x7FFFFF; Length = 0x800000; Offset = 0x20
>
> PciBus: Discovered PPB @ [07|00|00]
>
> PciBus: Discovered PCI @ [08|03|00]
> BAR[1]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x14
> BAR[4]: Type = PMem64; Alignment = 0x7FFFFF; Length = 0x800000; Offset = 0x20
>
> PciBus: Discovered PPB @ [0B|00|00]
>
> PciBus: Discovered PCI @ [0C|02|00]
> BAR[1]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x14
> BAR[4]: Type = PMem64; Alignment = 0x7FFFFF; Length = 0x800000; Offset = 0x20
>
> PciBus: Discovered PPB @ [0F|00|00]
>
> PciBus: Discovered PCI @ [10|04|00]
> BAR[1]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x14
> BAR[4]: Type = PMem64; Alignment = 0x7FFFFF; Length = 0x800000; Offset = 0x20
>
> PciBus: Discovered PCI @ [00|00|00]
>
> PciBus: Discovered PCI @ [00|01|00]
>
> PciBus: Discovered PCI @ [00|01|01]
> BAR[4]: Type = Io32; Alignment = 0xF; Length = 0x10; Offset = 0x20
>
> PciBus: Discovered PCI @ [00|01|03]
>
> PciBus: Discovered PCI @ [00|02|00]
> BAR[0]: Type = Mem32; Alignment = 0x3FFFFFF; Length = 0x4000000; Offset = 0x10
> BAR[1]: Type = Mem32; Alignment = 0x3FFFFFF; Length = 0x4000000; Offset = 0x14
> BAR[2]: Type = Mem32; Alignment = 0x1FFF; Length = 0x2000; Offset = 0x18
> BAR[3]: Type = Io32; Alignment = 0x1F; Length = 0x20; Offset = 0x1C
>
> PciBus: Discovered PCI @ [00|03|00]
>
> PciBus: Discovered PCI @ [00|04|00]
>
> PciBus: Discovered PCI @ [00|05|00]
>
> PciBus: Discovered PCI @ [00|06|00]
> BAR[1]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x14
> BAR[4]: Type = PMem64; Alignment = 0x7FFFFF; Length = 0x800000; Offset = 0x20
>
> PciBus: Discovered PPB @ [07|00|00]
>
> PciBus: Discovered PCI @ [08|03|00]
> BAR[1]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x14
> BAR[4]: Type = PMem64; Alignment = 0x7FFFFF; Length = 0x800000; Offset = 0x20
>
> PciBus: Discovered PPB @ [0B|00|00]
>
> PciBus: Discovered PCI @ [0C|02|00]
> BAR[1]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x14
> BAR[4]: Type = PMem64; Alignment = 0x7FFFFF; Length = 0x800000; Offset = 0x20
>
> PciBus: Discovered PPB @ [0F|00|00]
>
> PciBus: Discovered PCI @ [10|04|00]
> BAR[1]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x14
> BAR[4]: Type = PMem64; Alignment = 0x7FFFFF; Length = 0x800000; Offset = 0x20
>
> PciHostBridge: SubmitResources for PciRoot(0x0)
> I/O: Granularity/SpecificFlag = 0 / 01
> Length/Alignment = 0x1000 / 0xFFF
> Mem: Granularity/SpecificFlag = 32 / 00
> Length/Alignment = 0x8100000 / 0x3FFFFFF
> Mem: Granularity/SpecificFlag = 64 / 00
> Length/Alignment = 0x800000 / 0x7FFFFF
> PciBus: HostBridge->SubmitResources() - Success
> PciHostBridge: SubmitResources for PciRoot(0x7)
> Mem: Granularity/SpecificFlag = 32 / 00
> Length/Alignment = 0x100000 / 0xFFFFF
> Mem: Granularity/SpecificFlag = 64 / 00
> Length/Alignment = 0x800000 / 0x7FFFFF
> PciBus: HostBridge->SubmitResources() - Success
> PciHostBridge: SubmitResources for PciRoot(0xB)
> Mem: Granularity/SpecificFlag = 32 / 00
> Length/Alignment = 0x100000 / 0xFFFFF
> Mem: Granularity/SpecificFlag = 64 / 00
> Length/Alignment = 0x800000 / 0x7FFFFF
> PciBus: HostBridge->SubmitResources() - Success
> PciHostBridge: SubmitResources for PciRoot(0xF)
> Mem: Granularity/SpecificFlag = 32 / 00
> Length/Alignment = 0x100000 / 0xFFFFF
> Mem: Granularity/SpecificFlag = 64 / 00
> Length/Alignment = 0x800000 / 0x7FFFFF
> PciBus: HostBridge->SubmitResources() - Success
> PciHostBridge: NotifyPhase (AllocateResources)
> RootBridge: PciRoot(0x0)
> Mem: Base/Length/Alignment = 80000000/8100000/3FFFFFF - Success
> Mem64: Base/Length/Alignment = 800000000/800000/7FFFFF - Success
> I/O: Base/Length/Alignment = C000/1000/FFF - Success
> RootBridge: PciRoot(0x7)
> Mem64: Base/Length/Alignment = 800800000/800000/7FFFFF - Success
> Mem: Base/Length/Alignment = 88100000/100000/FFFFF - Success
> RootBridge: PciRoot(0xB)
> Mem64: Base/Length/Alignment = 801000000/800000/7FFFFF - Success
> Mem: Base/Length/Alignment = 88200000/100000/FFFFF - Success
> RootBridge: PciRoot(0xF)
> Mem64: Base/Length/Alignment = 801800000/800000/7FFFFF - Success
> Mem: Base/Length/Alignment = 88300000/100000/FFFFF - Success
> PciBus: HostBridge->NotifyPhase(AllocateResources) - Success
> PciBus: Resource Map for Root Bridge PciRoot(0x0)
> Type = Io16; Base = 0xC000; Length = 0x1000; Alignment = 0xFFF
> Base = 0xC000; Length = 0x20; Alignment = 0x1F; Owner = PCI [00|02|00:1C]
> Base = 0xC020; Length = 0x10; Alignment = 0xF; Owner = PCI [00|01|01:20]
> Type = Mem32; Base = 0x80000000; Length = 0x8100000; Alignment = 0x3FFFFFF
> Base = 0x80000000; Length = 0x4000000; Alignment = 0x3FFFFFF; Owner = PCI [00|02|00:14]
> Base = 0x84000000; Length = 0x4000000; Alignment = 0x3FFFFFF; Owner = PCI [00|02|00:10]
> Base = 0x88000000; Length = 0x2000; Alignment = 0x1FFF; Owner = PCI [00|02|00:18]
> Base = 0x88002000; Length = 0x1000; Alignment = 0xFFF; Owner = PCI [00|06|00:14]
> Type = Mem64; Base = 0x800000000; Length = 0x800000; Alignment = 0x7FFFFF
> Base = 0x800000000; Length = 0x800000; Alignment = 0x7FFFFF; Owner = PCI [00|06|00:20]; Type = PMem64
>
> PciBus: Resource Map for Root Bridge PciRoot(0x7)
> Type = Mem32; Base = 0x88100000; Length = 0x100000; Alignment = 0xFFFFF
> Base = 0x88100000; Length = 0x100000; Alignment = 0xFFFFF; Owner = PPB [07|00|00:**]
> Type = Mem64; Base = 0x800800000; Length = 0x800000; Alignment = 0x7FFFFF
> Base = 0x800800000; Length = 0x800000; Alignment = 0x7FFFFF; Owner = PPB [07|00|00:**]; Type = PMem64
>
> PciBus: Resource Map for Bridge [07|00|00]
> Type = Mem32; Base = 0x88100000; Length = 0x100000; Alignment = 0xFFFFF
> Base = 0x88100000; Length = 0x1000; Alignment = 0xFFF; Owner = PCI [08|03|00:14]
> Type = PMem64; Base = 0x800800000; Length = 0x800000; Alignment = 0x7FFFFF
> Base = 0x800800000; Length = 0x800000; Alignment = 0x7FFFFF; Owner = PCI [08|03|00:20]
>
> PciBus: Resource Map for Root Bridge PciRoot(0xB)
> Type = Mem32; Base = 0x88200000; Length = 0x100000; Alignment = 0xFFFFF
> Base = 0x88200000; Length = 0x100000; Alignment = 0xFFFFF; Owner = PPB [0B|00|00:**]
> Type = Mem64; Base = 0x801000000; Length = 0x800000; Alignment = 0x7FFFFF
> Base = 0x801000000; Length = 0x800000; Alignment = 0x7FFFFF; Owner = PPB [0B|00|00:**]; Type = PMem64
>
> PciBus: Resource Map for Bridge [0B|00|00]
> Type = Mem32; Base = 0x88200000; Length = 0x100000; Alignment = 0xFFFFF
> Base = 0x88200000; Length = 0x1000; Alignment = 0xFFF; Owner = PCI [0C|02|00:14]
> Type = PMem64; Base = 0x801000000; Length = 0x800000; Alignment = 0x7FFFFF
> Base = 0x801000000; Length = 0x800000; Alignment = 0x7FFFFF; Owner = PCI [0C|02|00:20]
>
> PciBus: Resource Map for Root Bridge PciRoot(0xF)
> Type = Mem32; Base = 0x88300000; Length = 0x100000; Alignment = 0xFFFFF
> Base = 0x88300000; Length = 0x100000; Alignment = 0xFFFFF; Owner = PPB [0F|00|00:**]
> Type = Mem64; Base = 0x801800000; Length = 0x800000; Alignment = 0x7FFFFF
> Base = 0x801800000; Length = 0x800000; Alignment = 0x7FFFFF; Owner = PPB [0F|00|00:**]; Type = PMem64
>
> PciBus: Resource Map for Bridge [0F|00|00]
> Type = Mem32; Base = 0x88300000; Length = 0x100000; Alignment = 0xFFFFF
> Base = 0x88300000; Length = 0x1000; Alignment = 0xFFF; Owner = PCI [10|04|00:14]
> Type = PMem64; Base = 0x801800000; Length = 0x800000; Alignment = 0x7FFFFF
> Base = 0x801800000; Length = 0x800000; Alignment = 0x7FFFFF; Owner = PCI [10|04|00:20]
For patches #2 through #5:
Tested-by: Laszlo Ersek <lersek@redhat.com>
I also ran "make check". The "check-qtest-i386" step (like all others) succeeded, which should cover patch #1 and #6 via "bios-tables-test.c". For those as well:
Tested-by: Laszlo Ersek <lersek@redhat.com>
Thanks
Laszlo
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [PATCH V4 0/6] pxb: fix 64-bit MMIO allocation
2016-07-01 13:57 ` [Qemu-devel] [PATCH V4 0/6] pxb: fix 64-bit MMIO allocation Laszlo Ersek
@ 2016-07-01 14:15 ` Marcel Apfelbaum
0 siblings, 0 replies; 9+ messages in thread
From: Marcel Apfelbaum @ 2016-07-01 14:15 UTC (permalink / raw)
To: Laszlo Ersek, qemu-devel; +Cc: ehabkost, mst, imammedo, pbonzini
On 07/01/2016 04:57 PM, Laszlo Ersek wrote:
> On 06/30/16 21:07, Marcel Apfelbaum wrote:
>> 64-bit BARs allocations fix for devices behind PXBs/PXB-PCIEs.
>>
>> In build_crs() the calculation and merging of the ranges already happens
>> in 64-bit, but the entry boundaries are silently truncated to 32-bit in the
>> call to aml_dword_memory(). Fix it by handling the 64-bit MMIO ranges separately.
>>
>> v3 -> v4:
>> Addressed Igor's comments (thanks for the productive review!)
>> - Split pxb test patch (previously patch 3/3) into the test itself (patch 1/6) and the blobs (patch 6/6).
>> - New patch declaring pxb/pxb-pxie as not hot-pluggable.
>> - Note that it does not solve the DSDT issue, but it is a prerequisite for the next patch.
>> - New patch solving the DSDT issue spotted by Igor.
>> - Using V=1 DIFF=diff make check does make it easier to review the ACPI changes, thanks.
>> - Patches 4 and 5 untouched (previously patches 1/3 and 2/3)
>>
>> v2 -> v3:
>> - split original series "pci: better support for 64-bit MMIO allocation" into 2 series:
>> - this is the first part dealing with correct 64-bit MMIO ACPI computation
>> - the second one will include 64-bit MMIO reservation for PCI hotplug
>> - Add pxb/pxb-pcie tests (Igor) - See diffs below (*)
>> - Re-based on latest master.
>>
>> v1 -> v2:
>> - resolved some styling issues (Laszlo)
>> - rebase on latest master (Laszlo)
>>
>> Thank you,
>> Marcel
>>
>> Marcel Apfelbaum (6):
>> tests/acpi: add pxb/pxb-pcie tests
>> hw/pxb: declare pxb devices as not hot-pluggable
>> hw/acpi: fix a DSDT table issue when a pxb is present.
>> acpi: refactor pxb crs computation
>> hw/apci: handle 64-bit MMIO regions correctly
>> tests/acpi: Add pxb/pxb-pcie tests blobs
>>
>> hw/i386/acpi-build.c | 131 ++++++++++++++++++++++++---------
>> hw/pci-bridge/pci_expander_bridge.c | 2 +
>> tests/acpi-test-data/pc/DSDT.pxb | Bin 0 -> 6280 bytes
>> tests/acpi-test-data/q35/DSDT.pxb_pcie | Bin 0 -> 9098 bytes
>> tests/bios-tables-test.c | 37 ++++++++++
>> 5 files changed, 134 insertions(+), 36 deletions(-)
>> create mode 100644 tests/acpi-test-data/pc/DSDT.pxb
>> create mode 100644 tests/acpi-test-data/q35/DSDT.pxb_pcie
>>
>
> I used the following commands to test (part of) the series:
>
>> VIRTIO10=1
>> ISO=/mnt/data/isos/iso-fedora/Fedora-Workstation-Live-x86_64-24-1.2.iso
>> CODE=/home/virt-images/OVMF_CODE.fd
>> TMPL=/home/virt-images/OVMF_VARS.fd
>> TFTP=/var/lib/dnsmasq
>> BF=shim.efi
>>
>> if [ $VIRTIO10 -eq 0 ]; then
>> MODERN=disable-legacy=off,disable-modern=on
>> else
>> MODERN=disable-legacy=on,disable-modern=off
>> fi
>>
>> cp $TMPL vars3.fd
>>
>> qemu-system-x86_64 \
>> -m 2048 \
>> -M pc \
>> -enable-kvm \
>> -device qxl-vga \
>> -drive if=pflash,readonly,format=raw,file=$CODE \
>> -drive if=pflash,format=raw,file=vars3.fd \
>> -drive id=cdrom,if=none,readonly,format=raw,cache=writethrough,file=$ISO \
>> \
>> -debugcon file:debug3.log \
>> -global isa-debugcon.iobase=0x402 \
>> \
>> -chardev stdio,signal=off,mux=on,id=char0 \
>> -mon chardev=char0,mode=readline,default \
>> -serial chardev:char0 \
>> \
>> -device pxb,bus=pci.0,id=bridge1,bus_nr=11 \
>> -device pxb,bus=pci.0,id=bridge2,bus_nr=7 \
>> -device pxb,bus=pci.0,id=bridge3,bus_nr=15 \
>> \
>> -device virtio-scsi-pci,id=scsi0,$MODERN,bus=pci.0 \
>> -device scsi-cd,bus=scsi0.0,drive=cdrom,bootindex=1 \
>> \
>> -netdev user,id=netdev0,hostfwd=tcp:127.0.0.1:2227-:22,tftp=$TFTP,bootfile=$BF,net=10.0.2.0/24 \
>> -device virtio-net-pci,netdev=netdev0,romfile=,$MODERN,bootindex=2,bus=bridge1,addr=2 \
>> \
>> -netdev user,id=netdev1,hostfwd=tcp:127.0.0.1:2228-:22,net=10.0.3.0/24 \
>> -device virtio-net-pci,netdev=netdev1,romfile=,$MODERN,bootindex=3,bus=bridge2,addr=3 \
>> \
>> -netdev user,id=netdev2,hostfwd=tcp:127.0.0.1:2229-:22,net=10.0.4.0/24 \
>> -device virtio-net-pci,netdev=netdev2,romfile=,$MODERN,bootindex=4,bus=bridge3,addr=4 \
>> \
>> -global PIIX4_PM.disable_s3=0 \
>>
>
> This is /proc/iomem from within the guest:
>
>> 00000000-00000fff : reserved
>> 00001000-0009ffff : System RAM
>> 000a0000-000bffff : PCI Bus 0000:00
>> 000f0000-000fffff : System ROM
>> 00100000-007fffff : System RAM
>> 00800000-00807fff : ACPI Non-volatile Storage
>> 00808000-0080ffff : System RAM
>> 00810000-008fffff : ACPI Non-volatile Storage
>> 00900000-7e529017 : System RAM
>> 02000000-027d3cf3 : Kernel code
>> 027d3cf4-02d4dfff : Kernel data
>> 02edc000-0305dfff : Kernel bss
>> 7e529018-7e532857 : System RAM
>> 7e532858-7e800fff : System RAM
>> 7e801000-7e820fff : ACPI Non-volatile Storage
>> 7e821000-7e84afff : reserved
>> 7e84b000-7ebe1fff : System RAM
>> 7ebe2000-7ebfdfff : reserved
>> 7ebfe000-7ec22fff : System RAM
>> 7ec23000-7ec35fff : reserved
>> 7ec36000-7ec99fff : System RAM
>> 7ec9a000-7ee16fff : reserved
>> 7ee17000-7fe96fff : System RAM
>> 7fe97000-7feeefff : reserved
>> 7feef000-7fef6fff : ACPI Tables
>> 7fef7000-7fefafff : ACPI Non-volatile Storage
>> 7fefb000-7ffcffff : System RAM
>> 7ffd0000-7ffeffff : reserved
>> 7fff0000-7fffffff : System RAM
>> 80000000-880fffff : PCI Bus 0000:00
>> 80000000-83ffffff : 0000:00:02.0
>> 84000000-87ffffff : 0000:00:02.0
>> 88000000-88001fff : 0000:00:02.0
>> 88002000-88002fff : 0000:00:06.0
>> 88010000-8801ffff : 0000:00:02.0
>> 88100000-881fffff : PCI Bus 0000:07
>> 88100000-881fffff : PCI Bus 0000:08
>> 88100000-88100fff : 0000:08:03.0
>> 88200000-882fffff : PCI Bus 0000:0b
>> 88200000-882fffff : PCI Bus 0000:0c
>> 88200000-88200fff : 0000:0c:02.0
>> 88300000-883fffff : PCI Bus 0000:0f
>> 88300000-883fffff : PCI Bus 0000:10
>> 88300000-88300fff : 0000:10:04.0
>> 88400000-febfffff : PCI Bus 0000:00
>> fec00000-fec003ff : IOAPIC 0
>> fed00000-fed003ff : HPET 0
>> fed00000-fed003ff : PNP0103:00
>> fee00000-fee00fff : Local APIC
>> ffe00000-ffffffff : reserved
>> 800000000-8007fffff : PCI Bus 0000:00
>> 800000000-8007fffff : 0000:00:06.0
>> 800000000-8007fffff : virtio-pci-modern
>> 800800000-800ffffff : PCI Bus 0000:07
>> 800800000-800ffffff : PCI Bus 0000:08
>> 800800000-800ffffff : 0000:08:03.0
>> 800800000-800ffffff : virtio-pci-modern
>> 801000000-8017fffff : PCI Bus 0000:0b
>> 801000000-8017fffff : PCI Bus 0000:0c
>> 801000000-8017fffff : 0000:0c:02.0
>> 801000000-8017fffff : virtio-pci-modern
>> 801800000-801ffffff : PCI Bus 0000:0f
>> 801800000-801ffffff : PCI Bus 0000:10
>> 801800000-801ffffff : 0000:10:04.0
>> 801800000-801ffffff : virtio-pci-modern
>
> It looks good to me. I also checked the _CRS objects in the DSDT in the guest (cursorily), it seemed okay.
>
> Guest dmesg contains no problems.
>
> The virtio-scsi CD obviously worked (booted Fedora 24 Live off of it). I also logged into the guest through all three NICs, with ssh.
>
> Below an excerpt from the OVMF debug log -- it appears consistent with the guest's /proc/iomem:
>
>> PciHostBridgeGetRootBridges: 3 extra root buses reported by QEMU
>> InitRootBridge: populated root bus 0, with room for 6 subordinate bus(es)
>> InitRootBridge: populated root bus 7, with room for 3 subordinate bus(es)
>> InitRootBridge: populated root bus 11, with room for 3 subordinate bus(es)
>> InitRootBridge: populated root bus 15, with room for 240 subordinate bus(es)
>> RootBridge: PciRoot(0x0)
>> Support/Attr: 70069 / 70069
>> DmaAbove4G: No
>> NoExtConfSpace: Yes
>> AllocAttr: 3 (CombineMemPMem Mem64Decode)
>> Bus: 0 - 6
>> Io: C000 - FFFF
>> Mem: 80000000 - FBFFFFFF
>> MemAbove4G: 800000000 - FFFFFFFFF
>> PMem: FFFFFFFFFFFFFFFF - 0
>> PMemAbove4G: FFFFFFFFFFFFFFFF - 0
>> PciHostBridgeDxe: IntersectMemoryDescriptor: add [800000000, 1000000000): Success
>> RootBridge: PciRoot(0x7)
>> Support/Attr: 70069 / 70069
>> DmaAbove4G: No
>> NoExtConfSpace: Yes
>> AllocAttr: 3 (CombineMemPMem Mem64Decode)
>> Bus: 7 - A
>> Io: C000 - FFFF
>> Mem: 80000000 - FBFFFFFF
>> MemAbove4G: 800000000 - FFFFFFFFF
>> PMem: FFFFFFFFFFFFFFFF - 0
>> PMemAbove4G: FFFFFFFFFFFFFFFF - 0
>> RootBridge: PciRoot(0xB)
>> Support/Attr: 70069 / 70069
>> DmaAbove4G: No
>> NoExtConfSpace: Yes
>> AllocAttr: 3 (CombineMemPMem Mem64Decode)
>> Bus: B - E
>> Io: C000 - FFFF
>> Mem: 80000000 - FBFFFFFF
>> MemAbove4G: 800000000 - FFFFFFFFF
>> PMem: FFFFFFFFFFFFFFFF - 0
>> PMemAbove4G: FFFFFFFFFFFFFFFF - 0
>> RootBridge: PciRoot(0xF)
>> Support/Attr: 70069 / 70069
>> DmaAbove4G: No
>> NoExtConfSpace: Yes
>> AllocAttr: 3 (CombineMemPMem Mem64Decode)
>> Bus: F - FF
>> Io: C000 - FFFF
>> Mem: 80000000 - FBFFFFFF
>> MemAbove4G: 800000000 - FFFFFFFFF
>> PMem: FFFFFFFFFFFFFFFF - 0
>> PMemAbove4G: FFFFFFFFFFFFFFFF - 0
>>
>> [...]
>>
>> PCI Bus First Scanning
>> PciBus: Discovered PCI @ [00|00|00]
>>
>> PciBus: Discovered PCI @ [00|01|00]
>>
>> PciBus: Discovered PCI @ [00|01|01]
>> BAR[4]: Type = Io32; Alignment = 0xF; Length = 0x10; Offset = 0x20
>>
>> PciBus: Discovered PCI @ [00|01|03]
>>
>> PciBus: Discovered PCI @ [00|02|00]
>> BAR[0]: Type = Mem32; Alignment = 0x3FFFFFF; Length = 0x4000000; Offset = 0x10
>> BAR[1]: Type = Mem32; Alignment = 0x3FFFFFF; Length = 0x4000000; Offset = 0x14
>> BAR[2]: Type = Mem32; Alignment = 0x1FFF; Length = 0x2000; Offset = 0x18
>> BAR[3]: Type = Io32; Alignment = 0x1F; Length = 0x20; Offset = 0x1C
>>
>> PciBus: Discovered PCI @ [00|03|00]
>>
>> PciBus: Discovered PCI @ [00|04|00]
>>
>> PciBus: Discovered PCI @ [00|05|00]
>>
>> PciBus: Discovered PCI @ [00|06|00]
>> BAR[1]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x14
>> BAR[4]: Type = PMem64; Alignment = 0x7FFFFF; Length = 0x800000; Offset = 0x20
>>
>> PciBus: Discovered PPB @ [07|00|00]
>>
>> PciBus: Discovered PCI @ [08|03|00]
>> BAR[1]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x14
>> BAR[4]: Type = PMem64; Alignment = 0x7FFFFF; Length = 0x800000; Offset = 0x20
>>
>> PciBus: Discovered PPB @ [0B|00|00]
>>
>> PciBus: Discovered PCI @ [0C|02|00]
>> BAR[1]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x14
>> BAR[4]: Type = PMem64; Alignment = 0x7FFFFF; Length = 0x800000; Offset = 0x20
>>
>> PciBus: Discovered PPB @ [0F|00|00]
>>
>> PciBus: Discovered PCI @ [10|04|00]
>> BAR[1]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x14
>> BAR[4]: Type = PMem64; Alignment = 0x7FFFFF; Length = 0x800000; Offset = 0x20
>>
>> PciBus: Discovered PCI @ [00|00|00]
>>
>> PciBus: Discovered PCI @ [00|01|00]
>>
>> PciBus: Discovered PCI @ [00|01|01]
>> BAR[4]: Type = Io32; Alignment = 0xF; Length = 0x10; Offset = 0x20
>>
>> PciBus: Discovered PCI @ [00|01|03]
>>
>> PciBus: Discovered PCI @ [00|02|00]
>> BAR[0]: Type = Mem32; Alignment = 0x3FFFFFF; Length = 0x4000000; Offset = 0x10
>> BAR[1]: Type = Mem32; Alignment = 0x3FFFFFF; Length = 0x4000000; Offset = 0x14
>> BAR[2]: Type = Mem32; Alignment = 0x1FFF; Length = 0x2000; Offset = 0x18
>> BAR[3]: Type = Io32; Alignment = 0x1F; Length = 0x20; Offset = 0x1C
>>
>> PciBus: Discovered PCI @ [00|03|00]
>>
>> PciBus: Discovered PCI @ [00|04|00]
>>
>> PciBus: Discovered PCI @ [00|05|00]
>>
>> PciBus: Discovered PCI @ [00|06|00]
>> BAR[1]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x14
>> BAR[4]: Type = PMem64; Alignment = 0x7FFFFF; Length = 0x800000; Offset = 0x20
>>
>> PciBus: Discovered PPB @ [07|00|00]
>>
>> PciBus: Discovered PCI @ [08|03|00]
>> BAR[1]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x14
>> BAR[4]: Type = PMem64; Alignment = 0x7FFFFF; Length = 0x800000; Offset = 0x20
>>
>> PciBus: Discovered PPB @ [0B|00|00]
>>
>> PciBus: Discovered PCI @ [0C|02|00]
>> BAR[1]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x14
>> BAR[4]: Type = PMem64; Alignment = 0x7FFFFF; Length = 0x800000; Offset = 0x20
>>
>> PciBus: Discovered PPB @ [0F|00|00]
>>
>> PciBus: Discovered PCI @ [10|04|00]
>> BAR[1]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x14
>> BAR[4]: Type = PMem64; Alignment = 0x7FFFFF; Length = 0x800000; Offset = 0x20
>>
>> PciHostBridge: SubmitResources for PciRoot(0x0)
>> I/O: Granularity/SpecificFlag = 0 / 01
>> Length/Alignment = 0x1000 / 0xFFF
>> Mem: Granularity/SpecificFlag = 32 / 00
>> Length/Alignment = 0x8100000 / 0x3FFFFFF
>> Mem: Granularity/SpecificFlag = 64 / 00
>> Length/Alignment = 0x800000 / 0x7FFFFF
>> PciBus: HostBridge->SubmitResources() - Success
>> PciHostBridge: SubmitResources for PciRoot(0x7)
>> Mem: Granularity/SpecificFlag = 32 / 00
>> Length/Alignment = 0x100000 / 0xFFFFF
>> Mem: Granularity/SpecificFlag = 64 / 00
>> Length/Alignment = 0x800000 / 0x7FFFFF
>> PciBus: HostBridge->SubmitResources() - Success
>> PciHostBridge: SubmitResources for PciRoot(0xB)
>> Mem: Granularity/SpecificFlag = 32 / 00
>> Length/Alignment = 0x100000 / 0xFFFFF
>> Mem: Granularity/SpecificFlag = 64 / 00
>> Length/Alignment = 0x800000 / 0x7FFFFF
>> PciBus: HostBridge->SubmitResources() - Success
>> PciHostBridge: SubmitResources for PciRoot(0xF)
>> Mem: Granularity/SpecificFlag = 32 / 00
>> Length/Alignment = 0x100000 / 0xFFFFF
>> Mem: Granularity/SpecificFlag = 64 / 00
>> Length/Alignment = 0x800000 / 0x7FFFFF
>> PciBus: HostBridge->SubmitResources() - Success
>> PciHostBridge: NotifyPhase (AllocateResources)
>> RootBridge: PciRoot(0x0)
>> Mem: Base/Length/Alignment = 80000000/8100000/3FFFFFF - Success
>> Mem64: Base/Length/Alignment = 800000000/800000/7FFFFF - Success
>> I/O: Base/Length/Alignment = C000/1000/FFF - Success
>> RootBridge: PciRoot(0x7)
>> Mem64: Base/Length/Alignment = 800800000/800000/7FFFFF - Success
>> Mem: Base/Length/Alignment = 88100000/100000/FFFFF - Success
>> RootBridge: PciRoot(0xB)
>> Mem64: Base/Length/Alignment = 801000000/800000/7FFFFF - Success
>> Mem: Base/Length/Alignment = 88200000/100000/FFFFF - Success
>> RootBridge: PciRoot(0xF)
>> Mem64: Base/Length/Alignment = 801800000/800000/7FFFFF - Success
>> Mem: Base/Length/Alignment = 88300000/100000/FFFFF - Success
>> PciBus: HostBridge->NotifyPhase(AllocateResources) - Success
>> PciBus: Resource Map for Root Bridge PciRoot(0x0)
>> Type = Io16; Base = 0xC000; Length = 0x1000; Alignment = 0xFFF
>> Base = 0xC000; Length = 0x20; Alignment = 0x1F; Owner = PCI [00|02|00:1C]
>> Base = 0xC020; Length = 0x10; Alignment = 0xF; Owner = PCI [00|01|01:20]
>> Type = Mem32; Base = 0x80000000; Length = 0x8100000; Alignment = 0x3FFFFFF
>> Base = 0x80000000; Length = 0x4000000; Alignment = 0x3FFFFFF; Owner = PCI [00|02|00:14]
>> Base = 0x84000000; Length = 0x4000000; Alignment = 0x3FFFFFF; Owner = PCI [00|02|00:10]
>> Base = 0x88000000; Length = 0x2000; Alignment = 0x1FFF; Owner = PCI [00|02|00:18]
>> Base = 0x88002000; Length = 0x1000; Alignment = 0xFFF; Owner = PCI [00|06|00:14]
>> Type = Mem64; Base = 0x800000000; Length = 0x800000; Alignment = 0x7FFFFF
>> Base = 0x800000000; Length = 0x800000; Alignment = 0x7FFFFF; Owner = PCI [00|06|00:20]; Type = PMem64
>>
>> PciBus: Resource Map for Root Bridge PciRoot(0x7)
>> Type = Mem32; Base = 0x88100000; Length = 0x100000; Alignment = 0xFFFFF
>> Base = 0x88100000; Length = 0x100000; Alignment = 0xFFFFF; Owner = PPB [07|00|00:**]
>> Type = Mem64; Base = 0x800800000; Length = 0x800000; Alignment = 0x7FFFFF
>> Base = 0x800800000; Length = 0x800000; Alignment = 0x7FFFFF; Owner = PPB [07|00|00:**]; Type = PMem64
>>
>> PciBus: Resource Map for Bridge [07|00|00]
>> Type = Mem32; Base = 0x88100000; Length = 0x100000; Alignment = 0xFFFFF
>> Base = 0x88100000; Length = 0x1000; Alignment = 0xFFF; Owner = PCI [08|03|00:14]
>> Type = PMem64; Base = 0x800800000; Length = 0x800000; Alignment = 0x7FFFFF
>> Base = 0x800800000; Length = 0x800000; Alignment = 0x7FFFFF; Owner = PCI [08|03|00:20]
>>
>> PciBus: Resource Map for Root Bridge PciRoot(0xB)
>> Type = Mem32; Base = 0x88200000; Length = 0x100000; Alignment = 0xFFFFF
>> Base = 0x88200000; Length = 0x100000; Alignment = 0xFFFFF; Owner = PPB [0B|00|00:**]
>> Type = Mem64; Base = 0x801000000; Length = 0x800000; Alignment = 0x7FFFFF
>> Base = 0x801000000; Length = 0x800000; Alignment = 0x7FFFFF; Owner = PPB [0B|00|00:**]; Type = PMem64
>>
>> PciBus: Resource Map for Bridge [0B|00|00]
>> Type = Mem32; Base = 0x88200000; Length = 0x100000; Alignment = 0xFFFFF
>> Base = 0x88200000; Length = 0x1000; Alignment = 0xFFF; Owner = PCI [0C|02|00:14]
>> Type = PMem64; Base = 0x801000000; Length = 0x800000; Alignment = 0x7FFFFF
>> Base = 0x801000000; Length = 0x800000; Alignment = 0x7FFFFF; Owner = PCI [0C|02|00:20]
>>
>> PciBus: Resource Map for Root Bridge PciRoot(0xF)
>> Type = Mem32; Base = 0x88300000; Length = 0x100000; Alignment = 0xFFFFF
>> Base = 0x88300000; Length = 0x100000; Alignment = 0xFFFFF; Owner = PPB [0F|00|00:**]
>> Type = Mem64; Base = 0x801800000; Length = 0x800000; Alignment = 0x7FFFFF
>> Base = 0x801800000; Length = 0x800000; Alignment = 0x7FFFFF; Owner = PPB [0F|00|00:**]; Type = PMem64
>>
>> PciBus: Resource Map for Bridge [0F|00|00]
>> Type = Mem32; Base = 0x88300000; Length = 0x100000; Alignment = 0xFFFFF
>> Base = 0x88300000; Length = 0x1000; Alignment = 0xFFF; Owner = PCI [10|04|00:14]
>> Type = PMem64; Base = 0x801800000; Length = 0x800000; Alignment = 0x7FFFFF
>> Base = 0x801800000; Length = 0x800000; Alignment = 0x7FFFFF; Owner = PCI [10|04|00:20]
>
> For patches #2 through #5:
>
> Tested-by: Laszlo Ersek <lersek@redhat.com>
>
> I also ran "make check". The "check-qtest-i386" step (like all others) succeeded, which should cover patch #1 and #6 via "bios-tables-test.c". For those as well:
>
> Tested-by: Laszlo Ersek <lersek@redhat.com>
Very appreciated!
Also for patch #5 that actually solves the problem:
Reported-by: Laszlo Ersek <lersek@redhat.com>
Thanks,
Marcel
>
> Thanks
> Laszlo
>
^ permalink raw reply [flat|nested] 9+ messages in thread