From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org
Cc: agraf@suse.de, benh@kernel.crashing.org, qemu-devel@nongnu.org,
qemu-ppc@nongnu.org, "Cédric Le Goater" <clg@kaod.org>,
"David Gibson" <david@gibson.dropbear.id.au>
Subject: [Qemu-devel] [PULL 01/23] ppc: Add a bunch of hypervisor SPRs to Book3s
Date: Fri, 1 Jul 2016 16:41:37 +1000 [thread overview]
Message-ID: <1467355319-28406-2-git-send-email-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <1467355319-28406-1-git-send-email-david@gibson.dropbear.id.au>
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
We don't give them a KVM reg number yet as no current KVM version
supports HV mode.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: SPRs AMOR,DAWR,DARWX were already included in commit f401dd32cb8e9]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/translate_init.c | 119 ++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 116 insertions(+), 3 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 08bdd07..d328455 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7793,15 +7793,116 @@ static void gen_spr_power5p_lpar(CPUPPCState *env)
spr_register_kvm(env, SPR_LPCR, "LPCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_LPCR, 0x00000000);
+ KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
}
+#if !defined(CONFIG_USER_ONLY)
+static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv hmer = tcg_temp_new();
+
+ gen_load_spr(hmer, sprn);
+ tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
+ gen_store_spr(sprn, hmer);
+ spr_store_dump_spr(sprn);
+ tcg_temp_free(hmer);
+}
+#endif
+
static void gen_spr_book3s_ids(CPUPPCState *env)
{
+ /* FIXME: Will need to deal with thread vs core only SPRs */
+
/* Processor identification */
- spr_register(env, SPR_PIR, "PIR",
+ spr_register_hv(env, SPR_PIR, "PIR",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_pir,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, NULL,
+ 0x00000000);
+ spr_register_hv(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_TSCR, "TSCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_HMER, "HMER",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_hmer,
+ 0x00000000);
+ spr_register_hv(env, SPR_HMEER, "HMEER",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_TFMR, "TFMR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_LPIDR, "LPIDR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_HFSCR, "HFSCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_MMCRC, "MMCRC",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_MMCRH, "MMCRH",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_HSRR0, "HSRR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_HSRR1, "HSRR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_HDAR, "HDAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_HDSISR, "HDSISR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_RMOR, "RMOR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_HRMOR, "HRMOR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
0x00000000);
}
@@ -8060,6 +8161,17 @@ static void gen_spr_power7_book4(CPUPPCState *env)
#endif
}
+static void gen_spr_power8_rpr(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ spr_register_hv(env, SPR_RPR, "RPR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000103070F1F3F);
+#endif
+}
+
static void init_proc_book3s_64(CPUPPCState *env, int version)
{
gen_spr_ne_601(env);
@@ -8117,6 +8229,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
gen_spr_vtb(env);
gen_spr_power8_ic(env);
gen_spr_power8_book4(env);
+ gen_spr_power8_rpr(env);
}
if (version < BOOK3S_CPU_POWER8) {
gen_spr_book3s_dbg(env);
--
2.7.4
next prev parent reply other threads:[~2016-07-01 6:40 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-01 6:41 [Qemu-devel] [PULL 00/23] ppc-for-2.7 queue 20160701 David Gibson
2016-07-01 6:41 ` David Gibson [this message]
2016-07-01 6:41 ` [Qemu-devel] [PULL 02/23] ppc: Update LPCR definitions David Gibson
2016-07-01 6:41 ` [Qemu-devel] [PULL 03/23] ppc: Use a helper to filter writes to LPCR David Gibson
2016-07-01 6:41 ` [Qemu-devel] [PULL 04/23] ppc: Fix conditions for delivering external interrupts to a guest David Gibson
2016-07-01 6:41 ` [Qemu-devel] [PULL 05/23] ppc: Enforce setting MSR:EE, IR and DR when MSR:PR is set David Gibson
2016-07-09 0:43 ` [Qemu-devel] [Qemu-ppc] " Mark Cave-Ayland
2016-07-09 2:46 ` Benjamin Herrenschmidt
2016-07-09 2:52 ` Benjamin Herrenschmidt
2016-07-09 3:00 ` Benjamin Herrenschmidt
2016-07-09 3:08 ` Benjamin Herrenschmidt
2016-07-09 3:22 ` [Qemu-devel] [PATCH] ppc: Fix support for odd MSR combinations Benjamin Herrenschmidt
2016-07-09 3:40 ` Benjamin Herrenschmidt
2016-07-09 3:41 ` [Qemu-devel] [PATCH v2] " Benjamin Herrenschmidt
2016-07-09 3:42 ` Benjamin Herrenschmidt
2016-07-09 9:56 ` Mark Cave-Ayland
2016-07-11 1:55 ` David Gibson
2016-07-11 18:30 ` Mark Cave-Ayland
2016-07-12 0:57 ` David Gibson
2016-07-09 9:04 ` [Qemu-devel] [Qemu-ppc] [PULL 05/23] ppc: Enforce setting MSR:EE, IR and DR when MSR:PR is set Mark Cave-Ayland
2016-07-09 8:16 ` Cédric Le Goater
2016-07-09 8:25 ` Benjamin Herrenschmidt
2016-07-09 8:28 ` Cédric Le Goater
2016-07-01 6:41 ` [Qemu-devel] [PULL 06/23] ppc: Initial HDEC support David Gibson
2016-07-01 6:41 ` [Qemu-devel] [PULL 07/23] ppc: LPCR is a HV resource David Gibson
2016-07-01 6:41 ` [Qemu-devel] [PULL 08/23] ppc: Print HSRR0/HSRR1 in "info registers" David Gibson
2016-07-01 6:41 ` [Qemu-devel] [PULL 09/23] hw/ppc/spapr: Add some missing hcall function set strings David Gibson
2016-07-01 6:41 ` [Qemu-devel] [PULL 10/23] spapr: fix write-past-end-of-array error in cpu core device init code David Gibson
2016-07-01 6:41 ` [Qemu-devel] [PULL 11/23] spapr: Restore support for older PowerPC CPU cores David Gibson
2016-07-01 6:41 ` [Qemu-devel] [PULL 12/23] target-ppc: Eliminate redundant and incorrect function booke206_page_size_to_tlb David Gibson
2016-07-01 6:41 ` [Qemu-devel] [PULL 13/23] ppc: Fix 64K pages support in full emulation David Gibson
2016-07-01 6:41 ` [Qemu-devel] [PULL 14/23] ppc/xics: Rename existing xics to xics_spapr David Gibson
2016-07-01 6:41 ` [Qemu-devel] [PULL 15/23] ppc/xics: Move SPAPR specific code to a separate file David Gibson
2016-07-01 6:41 ` [Qemu-devel] [PULL 16/23] ppc/xics: Implement H_IPOLL using an accessor David Gibson
2016-07-01 6:41 ` [Qemu-devel] [PULL 17/23] ppc/xics: Replace "icp" with "xics" in most places David Gibson
2016-07-01 6:41 ` [Qemu-devel] [PULL 18/23] target-ppc: gen_pause for instructions: yield, mdoio, mdoom, miso David Gibson
2016-07-01 6:41 ` [Qemu-devel] [PULL 19/23] spapr: Restore support for 970MP and POWER8NVL CPU cores David Gibson
2016-07-01 6:41 ` [Qemu-devel] [PULL 20/23] spapr: drop reference on child object during core realization David Gibson
2016-07-01 6:41 ` [Qemu-devel] [PULL 21/23] spapr: do proper error propagation in spapr_cpu_core_realize_child() David Gibson
2016-07-01 6:41 ` [Qemu-devel] [PULL 22/23] spapr: drop duplicate variable in spapr_core_release() David Gibson
2016-07-01 6:41 ` [Qemu-devel] [PULL 23/23] qmp: fix spapr example of query-hotpluggable-cpus David Gibson
2016-07-01 13:28 ` [Qemu-devel] [PULL 00/23] ppc-for-2.7 queue 20160701 Peter Maydell
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