From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50280) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bIy5T-0006oG-HG for qemu-devel@nongnu.org; Fri, 01 Jul 2016 09:02:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bIy5O-00050O-KK for qemu-devel@nongnu.org; Fri, 01 Jul 2016 09:02:26 -0400 From: Andrew Jones Date: Fri, 1 Jul 2016 15:02:08 +0200 Message-Id: <1467378129-23302-2-git-send-email-drjones@redhat.com> In-Reply-To: <1467378129-23302-1-git-send-email-drjones@redhat.com> References: <1467378129-23302-1-git-send-email-drjones@redhat.com> Subject: [Qemu-devel] [PATCH v2 1/2] gic: provide defines for v2/v3 targetlist sizes List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: peter.maydell@linaro.org Signed-off-by: Andrew Jones --- include/hw/intc/arm_gic.h | 3 +++ include/hw/intc/arm_gicv3_common.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h index 0971e37710dd6..42bb535fd4571 100644 --- a/include/hw/intc/arm_gic.h +++ b/include/hw/intc/arm_gic.h @@ -23,6 +23,9 @@ #include "arm_gic_common.h" +/* Number of SGI target-list bits */ +#define GIC_TARGETLIST_BITS 8 + #define TYPE_ARM_GIC "arm_gic" #define ARM_GIC(obj) \ OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC) diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h index f72e49922feb1..341a3118f0f44 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -35,6 +35,9 @@ #define GICV3_MAXIRQ 1020 #define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL) +/* Number of SGI target-list bits */ +#define GICV3_TARGETLIST_BITS 16 + /* Minimum BPR for Secure, or when security not enabled */ #define GIC_MIN_BPR 0 /* Minimum BPR for Nonsecure when security is enabled */ -- 2.7.4