From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53675) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bJ1sM-0002LK-SP for qemu-devel@nongnu.org; Fri, 01 Jul 2016 13:05:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bJ1sI-0005PK-Rn for qemu-devel@nongnu.org; Fri, 01 Jul 2016 13:05:10 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:35850) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bJ1sI-0005OC-HS for qemu-devel@nongnu.org; Fri, 01 Jul 2016 13:05:06 -0400 Received: by mail-pf0-x242.google.com with SMTP id i123so10452534pfg.3 for ; Fri, 01 Jul 2016 10:05:06 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Fri, 1 Jul 2016 10:04:39 -0700 Message-Id: <1467392693-22715-14-git-send-email-rth@twiddle.net> In-Reply-To: <1467392693-22715-1-git-send-email-rth@twiddle.net> References: <1467392693-22715-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v2 13/27] target-i386: emulate LOCK'ed INC using atomic helper List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: cota@braap.org, alex.bennee@linaro.org, pbonzini@redhat.com, peter.maydell@linaro.org, serge.fdrv@gmail.com From: "Emilio G. Cota" [rth: Merge gen_inc_locked back into gen_inc to share cc update.] Signed-off-by: Emilio G. Cota Message-Id: <1467054136-10430-14-git-send-email-cota@braap.org> Signed-off-by: Richard Henderson --- target-i386/translate.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 58bc954..3f10ff0 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -1362,21 +1362,23 @@ static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d) /* if d == OR_TMP0, it means memory operand (address in A0) */ static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c) { - if (d != OR_TMP0) { - gen_op_mov_v_reg(ot, cpu_T0, d); + if (s1->prefix & PREFIX_LOCK) { + tcg_gen_movi_tl(cpu_T0, c > 0 ? 1 : -1); + tcg_gen_atomic_add_fetch_tl(cpu_T0, cpu_A0, cpu_T0, + s1->mem_index, ot | MO_LE); } else { - gen_op_ld_v(s1, ot, cpu_T0, cpu_A0); + if (d != OR_TMP0) { + gen_op_mov_v_reg(ot, cpu_T0, d); + } else { + gen_op_ld_v(s1, ot, cpu_T0, cpu_A0); + } + tcg_gen_addi_tl(cpu_T0, cpu_T0, (c > 0 ? 1 : -1)); + gen_op_st_rm_T0_A0(s1, ot, d); } + gen_compute_eflags_c(s1, cpu_cc_src); - if (c > 0) { - tcg_gen_addi_tl(cpu_T0, cpu_T0, 1); - set_cc_op(s1, CC_OP_INCB + ot); - } else { - tcg_gen_addi_tl(cpu_T0, cpu_T0, -1); - set_cc_op(s1, CC_OP_DECB + ot); - } - gen_op_st_rm_T0_A0(s1, ot, d); tcg_gen_mov_tl(cpu_cc_dst, cpu_T0); + set_cc_op(s1, (c > 0 ? CC_OP_INCB : CC_OP_DECB) + ot); } static void gen_shift_flags(DisasContext *s, TCGMemOp ot, TCGv result, -- 2.5.5