From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53838) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bJ1sW-0002fn-RR for qemu-devel@nongnu.org; Fri, 01 Jul 2016 13:05:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bJ1sV-0005XF-4a for qemu-devel@nongnu.org; Fri, 01 Jul 2016 13:05:20 -0400 Received: from mail-pa0-x242.google.com ([2607:f8b0:400e:c03::242]:35562) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bJ1sU-0005X2-R1 for qemu-devel@nongnu.org; Fri, 01 Jul 2016 13:05:19 -0400 Received: by mail-pa0-x242.google.com with SMTP id hf6so10130307pac.2 for ; Fri, 01 Jul 2016 10:05:18 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Fri, 1 Jul 2016 10:04:53 -0700 Message-Id: <1467392693-22715-28-git-send-email-rth@twiddle.net> In-Reply-To: <1467392693-22715-1-git-send-email-rth@twiddle.net> References: <1467392693-22715-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v2 27/27] target-arm: remove EXCP_STREX + cpu_exclusive_{test, info} List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: cota@braap.org, alex.bennee@linaro.org, pbonzini@redhat.com, peter.maydell@linaro.org, serge.fdrv@gmail.com From: "Emilio G. Cota" The exception is not emitted anymore; remove it and the associated TCG variables. Signed-off-by: Emilio G. Cota Message-Id: <1467054136-10430-31-git-send-email-cota@braap.org> --- target-arm/cpu.h | 17 ++++++----------- target-arm/internals.h | 4 +--- target-arm/translate.c | 10 ---------- target-arm/translate.h | 4 ---- 4 files changed, 7 insertions(+), 28 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 7938ddc..0b2ed28 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -46,13 +46,12 @@ #define EXCP_BKPT 7 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ -#define EXCP_STREX 10 -#define EXCP_HVC 11 /* HyperVisor Call */ -#define EXCP_HYP_TRAP 12 -#define EXCP_SMC 13 /* Secure Monitor Call */ -#define EXCP_VIRQ 14 -#define EXCP_VFIQ 15 -#define EXCP_SEMIHOST 16 /* semihosting call (A64 only) */ +#define EXCP_HVC 10 /* HyperVisor Call */ +#define EXCP_HYP_TRAP 11 +#define EXCP_SMC 12 /* Secure Monitor Call */ +#define EXCP_VIRQ 13 +#define EXCP_VFIQ 14 +#define EXCP_SEMIHOST 15 /* semihosting call (A64 only) */ #define ARMV7M_EXCP_RESET 1 #define ARMV7M_EXCP_NMI 2 @@ -475,10 +474,6 @@ typedef struct CPUARMState { uint64_t exclusive_addr; uint64_t exclusive_val; uint64_t exclusive_high; -#if defined(CONFIG_USER_ONLY) - uint64_t exclusive_test; - uint32_t exclusive_info; -#endif /* iwMMXt coprocessor state. */ struct { diff --git a/target-arm/internals.h b/target-arm/internals.h index 466be0b..5ab3b28 100644 --- a/target-arm/internals.h +++ b/target-arm/internals.h @@ -46,8 +46,7 @@ static inline bool excp_is_internal(int excp) || excp == EXCP_HALTED || excp == EXCP_EXCEPTION_EXIT || excp == EXCP_KERNEL_TRAP - || excp == EXCP_SEMIHOST - || excp == EXCP_STREX; + || excp == EXCP_SEMIHOST; } /* Exception names for debug logging; note that not all of these @@ -63,7 +62,6 @@ static const char * const excnames[] = { [EXCP_BKPT] = "Breakpoint", [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", - [EXCP_STREX] = "QEMU intercept of STREX", [EXCP_HVC] = "Hypervisor Call", [EXCP_HYP_TRAP] = "Hypervisor Trap", [EXCP_SMC] = "Secure Monitor Call", diff --git a/target-arm/translate.c b/target-arm/translate.c index 2b3c34f..e8e8502 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -64,10 +64,6 @@ static TCGv_i32 cpu_R[16]; TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF; TCGv_i64 cpu_exclusive_addr; TCGv_i64 cpu_exclusive_val; -#ifdef CONFIG_USER_ONLY -TCGv_i64 cpu_exclusive_test; -TCGv_i32 cpu_exclusive_info; -#endif /* FIXME: These should be removed. */ static TCGv_i32 cpu_F0s, cpu_F1s; @@ -101,12 +97,6 @@ void arm_translate_init(void) offsetof(CPUARMState, exclusive_addr), "exclusive_addr"); cpu_exclusive_val = tcg_global_mem_new_i64(cpu_env, offsetof(CPUARMState, exclusive_val), "exclusive_val"); -#ifdef CONFIG_USER_ONLY - cpu_exclusive_test = tcg_global_mem_new_i64(cpu_env, - offsetof(CPUARMState, exclusive_test), "exclusive_test"); - cpu_exclusive_info = tcg_global_mem_new_i32(cpu_env, - offsetof(CPUARMState, exclusive_info), "exclusive_info"); -#endif a64_translate_init(); } diff --git a/target-arm/translate.h b/target-arm/translate.h index dbd7ac8..d4e205e 100644 --- a/target-arm/translate.h +++ b/target-arm/translate.h @@ -77,10 +77,6 @@ extern TCGv_env cpu_env; extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF; extern TCGv_i64 cpu_exclusive_addr; extern TCGv_i64 cpu_exclusive_val; -#ifdef CONFIG_USER_ONLY -extern TCGv_i64 cpu_exclusive_test; -extern TCGv_i32 cpu_exclusive_info; -#endif static inline int arm_dc_feature(DisasContext *dc, int feature) { -- 2.5.5