* [Qemu-devel] [PULL 4/6] aux: Rename aux.[ch] to auxbus.[ch] for the benefit of Windows
2016-07-07 13:48 [Qemu-devel] [PULL 0/6] target-arm queue Peter Maydell
` (2 preceding siblings ...)
2016-07-07 13:48 ` [Qemu-devel] [PULL 3/6] aux: fix break that wanted to break two levels out Peter Maydell
@ 2016-07-07 13:48 ` Peter Maydell
2016-07-07 13:48 ` [Qemu-devel] [PULL 5/6] hw/block/m25p80: fix resource leak Peter Maydell
` (2 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Peter Maydell @ 2016-07-07 13:48 UTC (permalink / raw)
To: qemu-devel
On Windows 'aux.*' is a reserved name and cannot be used for
filenames; see
https://msdn.microsoft.com/en-gb/library/windows/desktop/aa365247(v=vs.85).aspx
This prevents cloning the QEMU git repo on Windows:
C:\Java\sources\kvm> git clone https://github.com/qemu/qemu.git
Cloning into 'qemu'...
remote: Counting objects: 279563, done.
remote: Total 279563 (delta 0), reused 0 (delta 0), pack-reused 279563R
Receiving objects: 100% (279563/279563), 122.45 MiB | 3.52 MiB/s, done.
Resolving deltas: 100% (221942/221942), done.
Checking connectivity... done.
error: unable to create file hw/misc/aux.c (No such file or directory)
error: unable to create file include/hw/misc/aux.h (No such file or directory)
Checking out files: 100% (4795/4795), done.
fatal: unable to checkout working tree
warning: Clone succeeded, but checkout failed.
You can inspect what was checked out with 'git status'
and retry the checkout with 'git checkout -f HEAD'
(bug https://bugs.launchpad.net/bugs/1595240)
Rename the offending files for the benefit of Windows.
Reported-by: Алексей Курган <akurgan@yandex.ru>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Wei Huang <wei@redhat.com>
Tested-by: KONRAD Frederic <fred.konrad@greensocs.com>
Message-id: 1467377145-32385-1-git-send-email-peter.maydell@linaro.org
---
hw/display/dpcd.c | 2 +-
hw/misc/Makefile.objs | 2 +-
hw/misc/aux.c | 292 -------------------------------------------
hw/misc/auxbus.c | 292 +++++++++++++++++++++++++++++++++++++++++++
include/hw/display/xlnx_dp.h | 2 +-
include/hw/misc/aux.h | 128 -------------------
include/hw/misc/auxbus.h | 128 +++++++++++++++++++
7 files changed, 423 insertions(+), 423 deletions(-)
delete mode 100644 hw/misc/aux.c
create mode 100644 hw/misc/auxbus.c
delete mode 100644 include/hw/misc/aux.h
create mode 100644 include/hw/misc/auxbus.h
diff --git a/hw/display/dpcd.c b/hw/display/dpcd.c
index 5a36855..ce92ff6 100644
--- a/hw/display/dpcd.c
+++ b/hw/display/dpcd.c
@@ -28,7 +28,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
-#include "hw/misc/aux.h"
+#include "hw/misc/auxbus.h"
#include "hw/display/dpcd.h"
#ifndef DEBUG_DPCD
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 54020aa..4cfbd10 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -51,5 +51,5 @@ obj-$(CONFIG_MIPS_ITU) += mips_itu.o
obj-$(CONFIG_PVPANIC) += pvpanic.o
obj-$(CONFIG_EDU) += edu.o
obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o
-obj-$(CONFIG_AUX) += aux.o
+obj-$(CONFIG_AUX) += auxbus.o
obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o
diff --git a/hw/misc/aux.c b/hw/misc/aux.c
deleted file mode 100644
index 06e24ca..0000000
--- a/hw/misc/aux.c
+++ /dev/null
@@ -1,292 +0,0 @@
-/*
- * aux.c
- *
- * Copyright 2015 : GreenSocs Ltd
- * http://www.greensocs.com/ , email: info@greensocs.com
- *
- * Developed by :
- * Frederic Konrad <fred.konrad@greensocs.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option)any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- *
- */
-
-/*
- * This is an implementation of the AUX bus for VESA Display Port v1.1a.
- */
-
-#include "qemu/osdep.h"
-#include "qemu/log.h"
-#include "hw/misc/aux.h"
-#include "hw/i2c/i2c.h"
-#include "monitor/monitor.h"
-
-#ifndef DEBUG_AUX
-#define DEBUG_AUX 0
-#endif
-
-#define DPRINTF(fmt, ...) do { \
- if (DEBUG_AUX) { \
- qemu_log("aux: " fmt , ## __VA_ARGS__); \
- } \
-} while (0);
-
-#define TYPE_AUXTOI2C "aux-to-i2c-bridge"
-#define AUXTOI2C(obj) OBJECT_CHECK(AUXTOI2CState, (obj), TYPE_AUXTOI2C)
-
-static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent);
-static inline I2CBus *aux_bridge_get_i2c_bus(AUXTOI2CState *bridge);
-
-/* aux-bus implementation (internal not public) */
-static void aux_bus_class_init(ObjectClass *klass, void *data)
-{
- BusClass *k = BUS_CLASS(klass);
-
- /* AUXSlave has an MMIO so we need to change the way we print information
- * in monitor.
- */
- k->print_dev = aux_slave_dev_print;
-}
-
-AUXBus *aux_init_bus(DeviceState *parent, const char *name)
-{
- AUXBus *bus;
-
- bus = AUX_BUS(qbus_create(TYPE_AUX_BUS, parent, name));
- bus->bridge = AUXTOI2C(qdev_create(BUS(bus), TYPE_AUXTOI2C));
-
- /* Memory related. */
- bus->aux_io = g_malloc(sizeof(*bus->aux_io));
- memory_region_init(bus->aux_io, OBJECT(bus), "aux-io", (1 << 20));
- address_space_init(&bus->aux_addr_space, bus->aux_io, "aux-io");
- return bus;
-}
-
-static void aux_bus_map_device(AUXBus *bus, AUXSlave *dev, hwaddr addr)
-{
- memory_region_add_subregion(bus->aux_io, addr, dev->mmio);
-}
-
-static bool aux_bus_is_bridge(AUXBus *bus, DeviceState *dev)
-{
- return (dev == DEVICE(bus->bridge));
-}
-
-I2CBus *aux_get_i2c_bus(AUXBus *bus)
-{
- return aux_bridge_get_i2c_bus(bus->bridge);
-}
-
-AUXReply aux_request(AUXBus *bus, AUXCommand cmd, uint32_t address,
- uint8_t len, uint8_t *data)
-{
- AUXReply ret = AUX_NACK;
- I2CBus *i2c_bus = aux_get_i2c_bus(bus);
- size_t i;
- bool is_write = false;
-
- DPRINTF("request at address 0x%" PRIX32 ", command %u, len %u\n", address,
- cmd, len);
-
- switch (cmd) {
- /*
- * Forward the request on the AUX bus..
- */
- case WRITE_AUX:
- case READ_AUX:
- is_write = cmd == READ_AUX ? false : true;
- for (i = 0; i < len; i++) {
- if (!address_space_rw(&bus->aux_addr_space, address++,
- MEMTXATTRS_UNSPECIFIED, data++, 1,
- is_write)) {
- ret = AUX_I2C_ACK;
- } else {
- ret = AUX_NACK;
- break;
- }
- }
- break;
- /*
- * Classic I2C transactions..
- */
- case READ_I2C:
- case WRITE_I2C:
- is_write = cmd == READ_I2C ? false : true;
- if (i2c_bus_busy(i2c_bus)) {
- i2c_end_transfer(i2c_bus);
- }
-
- if (i2c_start_transfer(i2c_bus, address, is_write)) {
- ret = AUX_I2C_NACK;
- break;
- }
-
- ret = AUX_I2C_ACK;
- while (len > 0) {
- if (i2c_send_recv(i2c_bus, data++, is_write) < 0) {
- ret = AUX_I2C_NACK;
- break;
- }
- len--;
- }
- i2c_end_transfer(i2c_bus);
- break;
- /*
- * I2C MOT transactions.
- *
- * Here we send a start when:
- * - We didn't start transaction yet.
- * - We had a READ and we do a WRITE.
- * - We changed the address.
- */
- case WRITE_I2C_MOT:
- case READ_I2C_MOT:
- is_write = cmd == READ_I2C_MOT ? false : true;
- ret = AUX_I2C_NACK;
- if (!i2c_bus_busy(i2c_bus)) {
- /*
- * No transactions started..
- */
- if (i2c_start_transfer(i2c_bus, address, is_write)) {
- break;
- }
- } else if ((address != bus->last_i2c_address) ||
- (bus->last_transaction != cmd)) {
- /*
- * Transaction started but we need to restart..
- */
- i2c_end_transfer(i2c_bus);
- if (i2c_start_transfer(i2c_bus, address, is_write)) {
- break;
- }
- }
-
- bus->last_transaction = cmd;
- bus->last_i2c_address = address;
- while (len > 0) {
- if (i2c_send_recv(i2c_bus, data++, is_write) < 0) {
- i2c_end_transfer(i2c_bus);
- break;
- }
- len--;
- }
- if (len == 0) {
- ret = AUX_I2C_ACK;
- }
- break;
- default:
- DPRINTF("Not implemented!\n");
- return AUX_NACK;
- }
-
- DPRINTF("reply: %u\n", ret);
- return ret;
-}
-
-static const TypeInfo aux_bus_info = {
- .name = TYPE_AUX_BUS,
- .parent = TYPE_BUS,
- .instance_size = sizeof(AUXBus),
- .class_init = aux_bus_class_init
-};
-
-/* aux-i2c implementation (internal not public) */
-struct AUXTOI2CState {
- /*< private >*/
- DeviceState parent_obj;
-
- /*< public >*/
- I2CBus *i2c_bus;
-};
-
-static void aux_bridge_init(Object *obj)
-{
- AUXTOI2CState *s = AUXTOI2C(obj);
-
- s->i2c_bus = i2c_init_bus(DEVICE(obj), "aux-i2c");
-}
-
-static inline I2CBus *aux_bridge_get_i2c_bus(AUXTOI2CState *bridge)
-{
- return bridge->i2c_bus;
-}
-
-static const TypeInfo aux_to_i2c_type_info = {
- .name = TYPE_AUXTOI2C,
- .parent = TYPE_DEVICE,
- .instance_size = sizeof(AUXTOI2CState),
- .instance_init = aux_bridge_init
-};
-
-/* aux-slave implementation */
-static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent)
-{
- AUXBus *bus = AUX_BUS(qdev_get_parent_bus(dev));
- AUXSlave *s;
-
- /* Don't print anything if the device is I2C "bridge". */
- if (aux_bus_is_bridge(bus, dev)) {
- return;
- }
-
- s = AUX_SLAVE(dev);
-
- monitor_printf(mon, "%*smemory " TARGET_FMT_plx "/" TARGET_FMT_plx "\n",
- indent, "",
- object_property_get_int(OBJECT(s->mmio), "addr", NULL),
- memory_region_size(s->mmio));
-}
-
-DeviceState *aux_create_slave(AUXBus *bus, const char *type, uint32_t addr)
-{
- DeviceState *dev;
-
- dev = DEVICE(object_new(type));
- assert(dev);
- qdev_set_parent_bus(dev, &bus->qbus);
- qdev_init_nofail(dev);
- aux_bus_map_device(AUX_BUS(qdev_get_parent_bus(dev)), AUX_SLAVE(dev), addr);
- return dev;
-}
-
-void aux_init_mmio(AUXSlave *aux_slave, MemoryRegion *mmio)
-{
- assert(!aux_slave->mmio);
- aux_slave->mmio = mmio;
-}
-
-static void aux_slave_class_init(ObjectClass *klass, void *data)
-{
- DeviceClass *k = DEVICE_CLASS(klass);
-
- set_bit(DEVICE_CATEGORY_MISC, k->categories);
- k->bus_type = TYPE_AUX_BUS;
-}
-
-static const TypeInfo aux_slave_type_info = {
- .name = TYPE_AUX_SLAVE,
- .parent = TYPE_DEVICE,
- .instance_size = sizeof(AUXSlave),
- .abstract = true,
- .class_init = aux_slave_class_init,
-};
-
-static void aux_register_types(void)
-{
- type_register_static(&aux_bus_info);
- type_register_static(&aux_slave_type_info);
- type_register_static(&aux_to_i2c_type_info);
-}
-
-type_init(aux_register_types)
diff --git a/hw/misc/auxbus.c b/hw/misc/auxbus.c
new file mode 100644
index 0000000..e4a7ba4
--- /dev/null
+++ b/hw/misc/auxbus.c
@@ -0,0 +1,292 @@
+/*
+ * auxbus.c
+ *
+ * Copyright 2015 : GreenSocs Ltd
+ * http://www.greensocs.com/ , email: info@greensocs.com
+ *
+ * Developed by :
+ * Frederic Konrad <fred.konrad@greensocs.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option)any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+/*
+ * This is an implementation of the AUX bus for VESA Display Port v1.1a.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "hw/misc/auxbus.h"
+#include "hw/i2c/i2c.h"
+#include "monitor/monitor.h"
+
+#ifndef DEBUG_AUX
+#define DEBUG_AUX 0
+#endif
+
+#define DPRINTF(fmt, ...) do { \
+ if (DEBUG_AUX) { \
+ qemu_log("aux: " fmt , ## __VA_ARGS__); \
+ } \
+} while (0);
+
+#define TYPE_AUXTOI2C "aux-to-i2c-bridge"
+#define AUXTOI2C(obj) OBJECT_CHECK(AUXTOI2CState, (obj), TYPE_AUXTOI2C)
+
+static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent);
+static inline I2CBus *aux_bridge_get_i2c_bus(AUXTOI2CState *bridge);
+
+/* aux-bus implementation (internal not public) */
+static void aux_bus_class_init(ObjectClass *klass, void *data)
+{
+ BusClass *k = BUS_CLASS(klass);
+
+ /* AUXSlave has an MMIO so we need to change the way we print information
+ * in monitor.
+ */
+ k->print_dev = aux_slave_dev_print;
+}
+
+AUXBus *aux_init_bus(DeviceState *parent, const char *name)
+{
+ AUXBus *bus;
+
+ bus = AUX_BUS(qbus_create(TYPE_AUX_BUS, parent, name));
+ bus->bridge = AUXTOI2C(qdev_create(BUS(bus), TYPE_AUXTOI2C));
+
+ /* Memory related. */
+ bus->aux_io = g_malloc(sizeof(*bus->aux_io));
+ memory_region_init(bus->aux_io, OBJECT(bus), "aux-io", (1 << 20));
+ address_space_init(&bus->aux_addr_space, bus->aux_io, "aux-io");
+ return bus;
+}
+
+static void aux_bus_map_device(AUXBus *bus, AUXSlave *dev, hwaddr addr)
+{
+ memory_region_add_subregion(bus->aux_io, addr, dev->mmio);
+}
+
+static bool aux_bus_is_bridge(AUXBus *bus, DeviceState *dev)
+{
+ return (dev == DEVICE(bus->bridge));
+}
+
+I2CBus *aux_get_i2c_bus(AUXBus *bus)
+{
+ return aux_bridge_get_i2c_bus(bus->bridge);
+}
+
+AUXReply aux_request(AUXBus *bus, AUXCommand cmd, uint32_t address,
+ uint8_t len, uint8_t *data)
+{
+ AUXReply ret = AUX_NACK;
+ I2CBus *i2c_bus = aux_get_i2c_bus(bus);
+ size_t i;
+ bool is_write = false;
+
+ DPRINTF("request at address 0x%" PRIX32 ", command %u, len %u\n", address,
+ cmd, len);
+
+ switch (cmd) {
+ /*
+ * Forward the request on the AUX bus..
+ */
+ case WRITE_AUX:
+ case READ_AUX:
+ is_write = cmd == READ_AUX ? false : true;
+ for (i = 0; i < len; i++) {
+ if (!address_space_rw(&bus->aux_addr_space, address++,
+ MEMTXATTRS_UNSPECIFIED, data++, 1,
+ is_write)) {
+ ret = AUX_I2C_ACK;
+ } else {
+ ret = AUX_NACK;
+ break;
+ }
+ }
+ break;
+ /*
+ * Classic I2C transactions..
+ */
+ case READ_I2C:
+ case WRITE_I2C:
+ is_write = cmd == READ_I2C ? false : true;
+ if (i2c_bus_busy(i2c_bus)) {
+ i2c_end_transfer(i2c_bus);
+ }
+
+ if (i2c_start_transfer(i2c_bus, address, is_write)) {
+ ret = AUX_I2C_NACK;
+ break;
+ }
+
+ ret = AUX_I2C_ACK;
+ while (len > 0) {
+ if (i2c_send_recv(i2c_bus, data++, is_write) < 0) {
+ ret = AUX_I2C_NACK;
+ break;
+ }
+ len--;
+ }
+ i2c_end_transfer(i2c_bus);
+ break;
+ /*
+ * I2C MOT transactions.
+ *
+ * Here we send a start when:
+ * - We didn't start transaction yet.
+ * - We had a READ and we do a WRITE.
+ * - We changed the address.
+ */
+ case WRITE_I2C_MOT:
+ case READ_I2C_MOT:
+ is_write = cmd == READ_I2C_MOT ? false : true;
+ ret = AUX_I2C_NACK;
+ if (!i2c_bus_busy(i2c_bus)) {
+ /*
+ * No transactions started..
+ */
+ if (i2c_start_transfer(i2c_bus, address, is_write)) {
+ break;
+ }
+ } else if ((address != bus->last_i2c_address) ||
+ (bus->last_transaction != cmd)) {
+ /*
+ * Transaction started but we need to restart..
+ */
+ i2c_end_transfer(i2c_bus);
+ if (i2c_start_transfer(i2c_bus, address, is_write)) {
+ break;
+ }
+ }
+
+ bus->last_transaction = cmd;
+ bus->last_i2c_address = address;
+ while (len > 0) {
+ if (i2c_send_recv(i2c_bus, data++, is_write) < 0) {
+ i2c_end_transfer(i2c_bus);
+ break;
+ }
+ len--;
+ }
+ if (len == 0) {
+ ret = AUX_I2C_ACK;
+ }
+ break;
+ default:
+ DPRINTF("Not implemented!\n");
+ return AUX_NACK;
+ }
+
+ DPRINTF("reply: %u\n", ret);
+ return ret;
+}
+
+static const TypeInfo aux_bus_info = {
+ .name = TYPE_AUX_BUS,
+ .parent = TYPE_BUS,
+ .instance_size = sizeof(AUXBus),
+ .class_init = aux_bus_class_init
+};
+
+/* aux-i2c implementation (internal not public) */
+struct AUXTOI2CState {
+ /*< private >*/
+ DeviceState parent_obj;
+
+ /*< public >*/
+ I2CBus *i2c_bus;
+};
+
+static void aux_bridge_init(Object *obj)
+{
+ AUXTOI2CState *s = AUXTOI2C(obj);
+
+ s->i2c_bus = i2c_init_bus(DEVICE(obj), "aux-i2c");
+}
+
+static inline I2CBus *aux_bridge_get_i2c_bus(AUXTOI2CState *bridge)
+{
+ return bridge->i2c_bus;
+}
+
+static const TypeInfo aux_to_i2c_type_info = {
+ .name = TYPE_AUXTOI2C,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(AUXTOI2CState),
+ .instance_init = aux_bridge_init
+};
+
+/* aux-slave implementation */
+static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent)
+{
+ AUXBus *bus = AUX_BUS(qdev_get_parent_bus(dev));
+ AUXSlave *s;
+
+ /* Don't print anything if the device is I2C "bridge". */
+ if (aux_bus_is_bridge(bus, dev)) {
+ return;
+ }
+
+ s = AUX_SLAVE(dev);
+
+ monitor_printf(mon, "%*smemory " TARGET_FMT_plx "/" TARGET_FMT_plx "\n",
+ indent, "",
+ object_property_get_int(OBJECT(s->mmio), "addr", NULL),
+ memory_region_size(s->mmio));
+}
+
+DeviceState *aux_create_slave(AUXBus *bus, const char *type, uint32_t addr)
+{
+ DeviceState *dev;
+
+ dev = DEVICE(object_new(type));
+ assert(dev);
+ qdev_set_parent_bus(dev, &bus->qbus);
+ qdev_init_nofail(dev);
+ aux_bus_map_device(AUX_BUS(qdev_get_parent_bus(dev)), AUX_SLAVE(dev), addr);
+ return dev;
+}
+
+void aux_init_mmio(AUXSlave *aux_slave, MemoryRegion *mmio)
+{
+ assert(!aux_slave->mmio);
+ aux_slave->mmio = mmio;
+}
+
+static void aux_slave_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *k = DEVICE_CLASS(klass);
+
+ set_bit(DEVICE_CATEGORY_MISC, k->categories);
+ k->bus_type = TYPE_AUX_BUS;
+}
+
+static const TypeInfo aux_slave_type_info = {
+ .name = TYPE_AUX_SLAVE,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(AUXSlave),
+ .abstract = true,
+ .class_init = aux_slave_class_init,
+};
+
+static void aux_register_types(void)
+{
+ type_register_static(&aux_bus_info);
+ type_register_static(&aux_slave_type_info);
+ type_register_static(&aux_to_i2c_type_info);
+}
+
+type_init(aux_register_types)
diff --git a/include/hw/display/xlnx_dp.h b/include/hw/display/xlnx_dp.h
index d3a03f1..ee046a5 100644
--- a/include/hw/display/xlnx_dp.h
+++ b/include/hw/display/xlnx_dp.h
@@ -24,7 +24,7 @@
#include "hw/sysbus.h"
#include "ui/console.h"
-#include "hw/misc/aux.h"
+#include "hw/misc/auxbus.h"
#include "hw/i2c/i2c.h"
#include "hw/display/dpcd.h"
#include "hw/i2c/i2c-ddc.h"
diff --git a/include/hw/misc/aux.h b/include/hw/misc/aux.h
deleted file mode 100644
index 759c3bf..0000000
--- a/include/hw/misc/aux.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * aux.h
- *
- * Copyright (C)2014 : GreenSocs Ltd
- * http://www.greensocs.com/ , email: info@greensocs.com
- *
- * Developed by :
- * Frederic Konrad <fred.konrad@greensocs.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option)any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- *
- */
-
-#ifndef QEMU_AUX_H
-#define QEMU_AUX_H
-
-#include "hw/qdev.h"
-
-typedef struct AUXBus AUXBus;
-typedef struct AUXSlave AUXSlave;
-typedef enum AUXCommand AUXCommand;
-typedef enum AUXReply AUXReply;
-typedef struct AUXTOI2CState AUXTOI2CState;
-
-enum AUXCommand {
- WRITE_I2C = 0,
- READ_I2C = 1,
- WRITE_I2C_STATUS = 2,
- WRITE_I2C_MOT = 4,
- READ_I2C_MOT = 5,
- WRITE_AUX = 8,
- READ_AUX = 9
-};
-
-enum AUXReply {
- AUX_I2C_ACK = 0,
- AUX_NACK = 1,
- AUX_DEFER = 2,
- AUX_I2C_NACK = 4,
- AUX_I2C_DEFER = 8
-};
-
-#define TYPE_AUX_BUS "aux-bus"
-#define AUX_BUS(obj) OBJECT_CHECK(AUXBus, (obj), TYPE_AUX_BUS)
-
-struct AUXBus {
- /* < private > */
- BusState qbus;
-
- /* < public > */
- AUXSlave *current_dev;
- AUXSlave *dev;
- uint32_t last_i2c_address;
- AUXCommand last_transaction;
-
- AUXTOI2CState *bridge;
-
- MemoryRegion *aux_io;
- AddressSpace aux_addr_space;
-};
-
-#define TYPE_AUX_SLAVE "aux-slave"
-#define AUX_SLAVE(obj) \
- OBJECT_CHECK(AUXSlave, (obj), TYPE_AUX_SLAVE)
-
-struct AUXSlave {
- /* < private > */
- DeviceState parent_obj;
-
- /* < public > */
- MemoryRegion *mmio;
-};
-
-/**
- * aux_init_bus: Initialize an AUX bus.
- *
- * Returns the new AUX bus created.
- *
- * @parent The device where this bus is located.
- * @name The name of the bus.
- */
-AUXBus *aux_init_bus(DeviceState *parent, const char *name);
-
-/*
- * aux_request: Make a request on the bus.
- *
- * Returns the reply of the request.
- *
- * @bus Ths bus where the request happen.
- * @cmd The command requested.
- * @address The 20bits address of the slave.
- * @len The length of the read or write.
- * @data The data array which will be filled or read during transfer.
- */
-AUXReply aux_request(AUXBus *bus, AUXCommand cmd, uint32_t address,
- uint8_t len, uint8_t *data);
-
-/*
- * aux_get_i2c_bus: Get the i2c bus for I2C over AUX command.
- *
- * Returns the i2c bus associated to this AUX bus.
- *
- * @bus The AUX bus.
- */
-I2CBus *aux_get_i2c_bus(AUXBus *bus);
-
-/*
- * aux_init_mmio: Init an mmio for an AUX slave.
- *
- * @aux_slave The AUX slave.
- * @mmio The mmio to be registered.
- */
-void aux_init_mmio(AUXSlave *aux_slave, MemoryRegion *mmio);
-
-DeviceState *aux_create_slave(AUXBus *bus, const char *name, uint32_t addr);
-
-#endif /* !QEMU_AUX_H */
diff --git a/include/hw/misc/auxbus.h b/include/hw/misc/auxbus.h
new file mode 100644
index 0000000..af39db7
--- /dev/null
+++ b/include/hw/misc/auxbus.h
@@ -0,0 +1,128 @@
+/*
+ * auxbus.h
+ *
+ * Copyright (C)2014 : GreenSocs Ltd
+ * http://www.greensocs.com/ , email: info@greensocs.com
+ *
+ * Developed by :
+ * Frederic Konrad <fred.konrad@greensocs.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option)any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef QEMU_AUX_H
+#define QEMU_AUX_H
+
+#include "hw/qdev.h"
+
+typedef struct AUXBus AUXBus;
+typedef struct AUXSlave AUXSlave;
+typedef enum AUXCommand AUXCommand;
+typedef enum AUXReply AUXReply;
+typedef struct AUXTOI2CState AUXTOI2CState;
+
+enum AUXCommand {
+ WRITE_I2C = 0,
+ READ_I2C = 1,
+ WRITE_I2C_STATUS = 2,
+ WRITE_I2C_MOT = 4,
+ READ_I2C_MOT = 5,
+ WRITE_AUX = 8,
+ READ_AUX = 9
+};
+
+enum AUXReply {
+ AUX_I2C_ACK = 0,
+ AUX_NACK = 1,
+ AUX_DEFER = 2,
+ AUX_I2C_NACK = 4,
+ AUX_I2C_DEFER = 8
+};
+
+#define TYPE_AUX_BUS "aux-bus"
+#define AUX_BUS(obj) OBJECT_CHECK(AUXBus, (obj), TYPE_AUX_BUS)
+
+struct AUXBus {
+ /* < private > */
+ BusState qbus;
+
+ /* < public > */
+ AUXSlave *current_dev;
+ AUXSlave *dev;
+ uint32_t last_i2c_address;
+ AUXCommand last_transaction;
+
+ AUXTOI2CState *bridge;
+
+ MemoryRegion *aux_io;
+ AddressSpace aux_addr_space;
+};
+
+#define TYPE_AUX_SLAVE "aux-slave"
+#define AUX_SLAVE(obj) \
+ OBJECT_CHECK(AUXSlave, (obj), TYPE_AUX_SLAVE)
+
+struct AUXSlave {
+ /* < private > */
+ DeviceState parent_obj;
+
+ /* < public > */
+ MemoryRegion *mmio;
+};
+
+/**
+ * aux_init_bus: Initialize an AUX bus.
+ *
+ * Returns the new AUX bus created.
+ *
+ * @parent The device where this bus is located.
+ * @name The name of the bus.
+ */
+AUXBus *aux_init_bus(DeviceState *parent, const char *name);
+
+/*
+ * aux_request: Make a request on the bus.
+ *
+ * Returns the reply of the request.
+ *
+ * @bus Ths bus where the request happen.
+ * @cmd The command requested.
+ * @address The 20bits address of the slave.
+ * @len The length of the read or write.
+ * @data The data array which will be filled or read during transfer.
+ */
+AUXReply aux_request(AUXBus *bus, AUXCommand cmd, uint32_t address,
+ uint8_t len, uint8_t *data);
+
+/*
+ * aux_get_i2c_bus: Get the i2c bus for I2C over AUX command.
+ *
+ * Returns the i2c bus associated to this AUX bus.
+ *
+ * @bus The AUX bus.
+ */
+I2CBus *aux_get_i2c_bus(AUXBus *bus);
+
+/*
+ * aux_init_mmio: Init an mmio for an AUX slave.
+ *
+ * @aux_slave The AUX slave.
+ * @mmio The mmio to be registered.
+ */
+void aux_init_mmio(AUXSlave *aux_slave, MemoryRegion *mmio);
+
+DeviceState *aux_create_slave(AUXBus *bus, const char *name, uint32_t addr);
+
+#endif /* !QEMU_AUX_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [Qemu-devel] [PULL 6/6] i.MX: split the GPT timer implementation into per SOC definitions
2016-07-07 13:48 [Qemu-devel] [PULL 0/6] target-arm queue Peter Maydell
` (4 preceding siblings ...)
2016-07-07 13:48 ` [Qemu-devel] [PULL 5/6] hw/block/m25p80: fix resource leak Peter Maydell
@ 2016-07-07 13:48 ` Peter Maydell
2016-07-11 10:16 ` [Qemu-devel] [PULL 0/6] target-arm queue Peter Maydell
6 siblings, 0 replies; 8+ messages in thread
From: Peter Maydell @ 2016-07-07 13:48 UTC (permalink / raw)
To: qemu-devel
From: Jean-Christophe Dubois <jcd@tribudubois.net>
In various Freescale SOCs, the GPT timers can be configured to select
its input clock.
Depending on the SOC the set of available input clocks may vary.
The actual single GPT definition was no good enough and because of it
booting the sabrelite board with a i.MX6DL device tree would fail
because of an incorrect input clock definition for the i.MX6DL SOC.
This patch fixes the i.MX6DL boot failure by adding the ability to
define a different set of input clocks depending on the considered SOC.
A different class has been defined for i.MX25, i.MX31 and i.MX6 each with
its specific set of input clocks.
The patch has been tested by booting KZM, i.MX25 PDK, i.MX6Q sabrelite
and i.MX6DL sabrelite.
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: 1467325619-8374-1-git-send-email-jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: fixed spacing round '/' operator]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/fsl-imx25.c | 2 +-
hw/arm/fsl-imx31.c | 2 +-
hw/arm/fsl-imx6.c | 2 +-
hw/misc/imx6_ccm.c | 6 ++++
hw/timer/imx_gpt.c | 69 ++++++++++++++++++++++++++++++++++++++++++----
include/hw/misc/imx_ccm.h | 5 +++-
include/hw/timer/imx_gpt.h | 9 +++++-
7 files changed, 84 insertions(+), 11 deletions(-)
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
index 1a53e51..b4e358d 100644
--- a/hw/arm/fsl-imx25.c
+++ b/hw/arm/fsl-imx25.c
@@ -51,7 +51,7 @@ static void fsl_imx25_init(Object *obj)
}
for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
- object_initialize(&s->gpt[i], sizeof(s->gpt[i]), TYPE_IMX_GPT);
+ object_initialize(&s->gpt[i], sizeof(s->gpt[i]), TYPE_IMX25_GPT);
qdev_set_parent_bus(DEVICE(&s->gpt[i]), sysbus_get_default());
}
diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c
index b283b71..fe204ac 100644
--- a/hw/arm/fsl-imx31.c
+++ b/hw/arm/fsl-imx31.c
@@ -47,7 +47,7 @@ static void fsl_imx31_init(Object *obj)
qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
}
- object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX_GPT);
+ object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX31_GPT);
qdev_set_parent_bus(DEVICE(&s->gpt), sysbus_get_default());
for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
index ed392a9..6a1bf26 100644
--- a/hw/arm/fsl-imx6.c
+++ b/hw/arm/fsl-imx6.c
@@ -67,7 +67,7 @@ static void fsl_imx6_init(Object *obj)
object_property_add_child(obj, name, OBJECT(&s->uart[i]), NULL);
}
- object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX_GPT);
+ object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX6_GPT);
qdev_set_parent_bus(DEVICE(&s->gpt), sysbus_get_default());
object_property_add_child(obj, "gpt", OBJECT(&s->gpt), NULL);
diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c
index ec58eef..17e15d4 100644
--- a/hw/misc/imx6_ccm.c
+++ b/hw/misc/imx6_ccm.c
@@ -371,6 +371,12 @@ static uint32_t imx6_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
case CLK_32k:
freq = CKIL_FREQ;
break;
+ case CLK_HIGH:
+ freq = 24000000;
+ break;
+ case CLK_HIGH_DIV:
+ freq = 24000000 / 8;
+ break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
TYPE_IMX6_CCM, __func__, clock);
diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c
index 3c2f01a..82bc73c 100644
--- a/hw/timer/imx_gpt.c
+++ b/hw/timer/imx_gpt.c
@@ -14,7 +14,6 @@
#include "qemu/osdep.h"
#include "hw/timer/imx_gpt.h"
-#include "hw/misc/imx_ccm.h"
#include "qemu/main-loop.h"
#include "qemu/log.h"
@@ -81,7 +80,18 @@ static const VMStateDescription vmstate_imx_timer_gpt = {
}
};
-static const IMXClk imx_gpt_clocks[] = {
+static const IMXClk imx25_gpt_clocks[] = {
+ CLK_NONE, /* 000 No clock source */
+ CLK_IPG, /* 001 ipg_clk, 532MHz*/
+ CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */
+ CLK_NONE, /* 011 not defined */
+ CLK_32k, /* 100 ipg_clk_32k */
+ CLK_32k, /* 101 ipg_clk_32k */
+ CLK_32k, /* 110 ipg_clk_32k */
+ CLK_32k, /* 111 ipg_clk_32k */
+};
+
+static const IMXClk imx31_gpt_clocks[] = {
CLK_NONE, /* 000 No clock source */
CLK_IPG, /* 001 ipg_clk, 532MHz*/
CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */
@@ -92,12 +102,23 @@ static const IMXClk imx_gpt_clocks[] = {
CLK_NONE, /* 111 not defined */
};
+static const IMXClk imx6_gpt_clocks[] = {
+ CLK_NONE, /* 000 No clock source */
+ CLK_IPG, /* 001 ipg_clk, 532MHz*/
+ CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */
+ CLK_EXT, /* 011 External clock */
+ CLK_32k, /* 100 ipg_clk_32k */
+ CLK_HIGH_DIV, /* 101 reference clock / 8 */
+ CLK_NONE, /* 110 not defined */
+ CLK_HIGH, /* 111 reference clock */
+};
+
static void imx_gpt_set_freq(IMXGPTState *s)
{
uint32_t clksrc = extract32(s->cr, GPT_CR_CLKSRC_SHIFT, 3);
s->freq = imx_ccm_get_clock_frequency(s->ccm,
- imx_gpt_clocks[clksrc]) / (1 + s->pr);
+ s->clocks[clksrc]) / (1 + s->pr);
DPRINTF("Setting clksrc %d to frequency %d\n", clksrc, s->freq);
@@ -453,16 +474,52 @@ static void imx_gpt_class_init(ObjectClass *klass, void *data)
dc->desc = "i.MX general timer";
}
-static const TypeInfo imx_gpt_info = {
- .name = TYPE_IMX_GPT,
+static void imx25_gpt_init(Object *obj)
+{
+ IMXGPTState *s = IMX_GPT(obj);
+
+ s->clocks = imx25_gpt_clocks;
+}
+
+static void imx31_gpt_init(Object *obj)
+{
+ IMXGPTState *s = IMX_GPT(obj);
+
+ s->clocks = imx31_gpt_clocks;
+}
+
+static void imx6_gpt_init(Object *obj)
+{
+ IMXGPTState *s = IMX_GPT(obj);
+
+ s->clocks = imx6_gpt_clocks;
+}
+
+static const TypeInfo imx25_gpt_info = {
+ .name = TYPE_IMX25_GPT,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(IMXGPTState),
+ .instance_init = imx25_gpt_init,
.class_init = imx_gpt_class_init,
};
+static const TypeInfo imx31_gpt_info = {
+ .name = TYPE_IMX31_GPT,
+ .parent = TYPE_IMX25_GPT,
+ .instance_init = imx31_gpt_init,
+};
+
+static const TypeInfo imx6_gpt_info = {
+ .name = TYPE_IMX6_GPT,
+ .parent = TYPE_IMX25_GPT,
+ .instance_init = imx6_gpt_init,
+};
+
static void imx_gpt_register_types(void)
{
- type_register_static(&imx_gpt_info);
+ type_register_static(&imx25_gpt_info);
+ type_register_static(&imx31_gpt_info);
+ type_register_static(&imx6_gpt_info);
}
type_init(imx_gpt_register_types)
diff --git a/include/hw/misc/imx_ccm.h b/include/hw/misc/imx_ccm.h
index 48a7afa..33cbc09 100644
--- a/include/hw/misc/imx_ccm.h
+++ b/include/hw/misc/imx_ccm.h
@@ -46,7 +46,10 @@ typedef enum {
CLK_NONE,
CLK_IPG,
CLK_IPG_HIGH,
- CLK_32k
+ CLK_32k,
+ CLK_EXT,
+ CLK_HIGH_DIV,
+ CLK_HIGH,
} IMXClk;
typedef struct IMXCCMClass {
diff --git a/include/hw/timer/imx_gpt.h b/include/hw/timer/imx_gpt.h
index 461adbe..eac59b2 100644
--- a/include/hw/timer/imx_gpt.h
+++ b/include/hw/timer/imx_gpt.h
@@ -74,7 +74,12 @@
#define GPT_IR_OF3IE (1 << 2)
#define GPT_IR_ROVIE (1 << 5)
-#define TYPE_IMX_GPT "imx.gpt"
+#define TYPE_IMX25_GPT "imx25.gpt"
+#define TYPE_IMX31_GPT "imx31.gpt"
+#define TYPE_IMX6_GPT "imx6.gpt"
+
+#define TYPE_IMX_GPT TYPE_IMX25_GPT
+
#define IMX_GPT(obj) OBJECT_CHECK(IMXGPTState, (obj), TYPE_IMX_GPT)
typedef struct IMXGPTState{
@@ -103,6 +108,8 @@ typedef struct IMXGPTState{
uint32_t freq;
qemu_irq irq;
+
+ const IMXClk *clocks;
} IMXGPTState;
#endif /* IMX_GPT_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread