From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33688) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bLXHl-0007sT-NX for qemu-devel@nongnu.org; Fri, 08 Jul 2016 11:01:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bLXHk-0002FA-33 for qemu-devel@nongnu.org; Fri, 08 Jul 2016 11:01:45 -0400 Received: from mx1.redhat.com ([209.132.183.28]:54159) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bLXHj-0002F6-U0 for qemu-devel@nongnu.org; Fri, 08 Jul 2016 11:01:44 -0400 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 741DE7AE85 for ; Fri, 8 Jul 2016 15:01:43 +0000 (UTC) From: "Dr. David Alan Gilbert (git)" Date: Fri, 8 Jul 2016 16:01:35 +0100 Message-Id: <1467990099-27853-2-git-send-email-dgilbert@redhat.com> In-Reply-To: <1467990099-27853-1-git-send-email-dgilbert@redhat.com> References: <1467990099-27853-1-git-send-email-dgilbert@redhat.com> Subject: [Qemu-devel] [PATCH v4 1/5] x86: Provide TCG_PHYS_ADDR_BITS List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, pbonzini@redhat.com, ehabkost@redhat.com, marcel@redhat.com, mst@redhat.com, kraxel@redhat.com From: "Dr. David Alan Gilbert" Provide a constant for the number of address bits supported under TCG. Signed-off-by: Dr. David Alan Gilbert Suggested-by: Eduardo Habkost --- target-i386/cpu.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 474b0b9..b3162b7 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -1403,11 +1403,13 @@ uint64_t cpu_get_tsc(CPUX86State *env); /* XXX: This value should match the one returned by CPUID * and in exec.c */ # if defined(TARGET_X86_64) -# define PHYS_ADDR_MASK 0xffffffffffLL +# define TCG_PHYS_ADDR_BITS 40 # else -# define PHYS_ADDR_MASK 0xfffffffffLL +# define TCG_PHYS_ADDR_BITS 36 # endif +#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS) + #define cpu_init(cpu_model) CPU(cpu_x86_init(cpu_model)) #define cpu_signal_handler cpu_x86_signal_handler -- 2.7.4