From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33735) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bLXHu-0007xC-6D for qemu-devel@nongnu.org; Fri, 08 Jul 2016 11:01:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bLXHp-0002GG-2V for qemu-devel@nongnu.org; Fri, 08 Jul 2016 11:01:53 -0400 Received: from mx1.redhat.com ([209.132.183.28]:33818) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bLXHo-0002GC-R9 for qemu-devel@nongnu.org; Fri, 08 Jul 2016 11:01:49 -0400 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 5F5BD72676 for ; Fri, 8 Jul 2016 15:01:48 +0000 (UTC) From: "Dr. David Alan Gilbert (git)" Date: Fri, 8 Jul 2016 16:01:38 +0100 Message-Id: <1467990099-27853-5-git-send-email-dgilbert@redhat.com> In-Reply-To: <1467990099-27853-1-git-send-email-dgilbert@redhat.com> References: <1467990099-27853-1-git-send-email-dgilbert@redhat.com> Subject: [Qemu-devel] [PATCH v4 4/5] x86: fill high bits of mtrr mask List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, pbonzini@redhat.com, ehabkost@redhat.com, marcel@redhat.com, mst@redhat.com, kraxel@redhat.com From: "Dr. David Alan Gilbert" Fill the bits between 51..number-of-physical-address-bits in the MTRR_PHYSMASKn variable range mtrr masks so that they're consistent in the migration stream irrespective of the physical address space of the source VM in a migration. Signed-off-by: Dr. David Alan Gilbert Suggested-by: Paolo Bonzini --- include/hw/i386/pc.h | 5 +++++ target-i386/cpu.c | 1 + target-i386/cpu.h | 3 +++ target-i386/kvm.c | 28 +++++++++++++++++++++++++++- 4 files changed, 36 insertions(+), 1 deletion(-) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 2123532..7d9d03c 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -373,6 +373,11 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); .driver = "vmxnet3",\ .property = "romfile",\ .value = "",\ + },\ + {\ + .driver = TYPE_X86_CPU,\ + .property = "fill-mtrr-mask",\ + .value = "off",\ }, #define PC_COMPAT_2_5 \ diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 2cc5609..641c38b 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -3290,6 +3290,7 @@ static Property x86_cpu_properties[] = { DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), + DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, 0), DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0), DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0), diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 202f9a3..9d79146 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -1181,6 +1181,9 @@ struct X86CPU { /* Compatibility bits for old machine types: */ bool enable_cpuid_0xb; + /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ + bool fill_mtrr_mask; + /* Number of physical address bits supported */ uint32_t phys_bits; diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 6429205..6fe0f48 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -1935,6 +1935,7 @@ static int kvm_get_msrs(X86CPU *cpu) CPUX86State *env = &cpu->env; struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries; int ret, i; + uint64_t mtrr_top_bits; kvm_msr_buf_reset(cpu); @@ -2084,6 +2085,30 @@ static int kvm_get_msrs(X86CPU *cpu) } assert(ret == cpu->kvm_msr_buf->nmsrs); + /* + * MTRR masks: Each mask consists of 5 parts + * a 10..0: must be zero + * b 11 : valid bit + * c n-1.12: actual mask bits + * d 51..n: reserved must be zero + * e 63.52: reserved must be zero + * + * 'n' is the number of physical bits supported by the CPU and is + * apparently always <= 52. We know our 'n' but don't know what + * the destinations 'n' is; it might be smaller, in which case + * it masks (c) on loading. It might be larger, in which case + * we fill 'd' so that d..c is consistent irrespetive of the 'n' + * we're migrating to. + */ + + if (cpu->fill_mtrr_mask) { + QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52); + assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS); + mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits); + } else { + mtrr_top_bits = 0; + } + for (i = 0; i < ret; i++) { uint32_t index = msrs[i].index; switch (index) { @@ -2279,7 +2304,8 @@ static int kvm_get_msrs(X86CPU *cpu) break; case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1): if (index & 1) { - env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data; + env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data | + mtrr_top_bits; } else { env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data; } -- 2.7.4