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From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: Sat, 09 Jul 2016 13:08:15 +1000
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Subject: Re: [Qemu-devel] [Qemu-ppc] [PULL 05/23] ppc: Enforce setting
 MSR:EE, IR and DR when MSR:PR is set
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To: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>, David Gibson <david@gibson.dropbear.id.au>, peter.maydell@linaro.org
Cc: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, =?ISO-8859-1?Q?C=E9dric?= Le Goater <clg@kaod.org>

On Sat, 2016-07-09 at 13:00 +1000, Benjamin Herrenschmidt wrote:
> > Additionally,=C2=A0hreg_compute_mem_idx() will treat PR=3D1 as DR=3D1=
/IR=3D1
> > as well ! That means that if those old processors allow PR=3D1 and IR
> > or DR=3D0 and MacOS uses it, we do have a TLB coherency problem in
> > qemu.
>=20
> Wow, yes indeed, I see an MSR with PR=3D1 IR=3D0, IR=3D1 and EE=3D0 .. =
ugh.

Note that I see that happening with OS 9, but not with Darwin ... are
you sure about OS X ?

Cheers,
Ben.