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From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: Sat, 09 Jul 2016 13:40:03 +1000
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Subject: Re: [Qemu-devel] [PATCH] ppc: Fix support for odd MSR combinations
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To: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>, David Gibson <david@gibson.dropbear.id.au>, peter.maydell@linaro.org
Cc: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, =?ISO-8859-1?Q?C=E9dric?= Le Goater <clg@kaod.org>

On Sat, 2016-07-09 at 13:22 +1000, Benjamin Herrenschmidt wrote:
> MacOS uses an architecturally illegal MSR combination that
> seems nonetheless supported by 32-bit processors, which is
> to have MSR[PR]=3D1 and one or more of MSR[DR/IR/EE]=3D0.
>=20
> This adds support for it. To work properly we need to also
> properly include support for PR=3D1,{I,D}R=3D0 to the MMU index
> used by the qemu TLB.
>=20
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---

Oopps, little bug, v2 on its way:
+=C2=A0
=C2=A0=C2=A0=C2=A0if ((env->flags & PPC_64B) && ((value >> MSR_PR) & 1)) =
{

This should be insns_flags

> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0value |=3D (1 << =
MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR);
> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0}
> =C2=A0#endif