From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56512) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bN2xc-0005Lc-6Y for qemu-devel@nongnu.org; Tue, 12 Jul 2016 15:03:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bN2xa-0002kH-KB for qemu-devel@nongnu.org; Tue, 12 Jul 2016 15:03:12 -0400 Received: from mail-qk0-x241.google.com ([2607:f8b0:400d:c09::241]:36067) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bN2xa-0002jn-Fz for qemu-devel@nongnu.org; Tue, 12 Jul 2016 15:03:10 -0400 Received: by mail-qk0-x241.google.com with SMTP id q8so530478qke.3 for ; Tue, 12 Jul 2016 12:03:10 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Tue, 12 Jul 2016 12:02:12 -0700 Message-Id: <1468350138-9736-19-git-send-email-rth@twiddle.net> In-Reply-To: <1468350138-9736-1-git-send-email-rth@twiddle.net> References: <1468350138-9736-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PULL 18/24] target-sparc: Directly implement easy ldf/stf asis List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk Tested-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target-sparc/translate.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 0b29aff..2ea6964 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -2282,10 +2282,33 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) { DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEQ)); + TCGv_i32 d32; switch (da.type) { case GET_ASI_EXCP: break; + + case GET_ASI_DIRECT: + gen_address_mask(dc, addr); + switch (size) { + case 4: + d32 = gen_dest_fpr_F(dc); + tcg_gen_qemu_ld_i32(d32, addr, da.mem_idx, da.memop); + gen_store_fpr_F(dc, rd, d32); + break; + case 8: + tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx, da.memop); + break; + case 16: + tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx, da.memop); + tcg_gen_addi_tl(addr, addr, 8); + tcg_gen_qemu_ld_i64(cpu_fpr[rd/2+1], addr, da.mem_idx, da.memop); + break; + default: + g_assert_not_reached(); + } + break; + default: { TCGv_i32 r_asi = tcg_const_i32(da.asi); @@ -2306,10 +2329,32 @@ static void gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) { DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEQ)); + TCGv_i32 d32; switch (da.type) { case GET_ASI_EXCP: break; + + case GET_ASI_DIRECT: + gen_address_mask(dc, addr); + switch (size) { + case 4: + d32 = gen_load_fpr_F(dc, rd); + tcg_gen_qemu_st_i32(d32, addr, da.mem_idx, da.memop); + break; + case 8: + tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, da.memop); + break; + case 16: + tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, da.memop); + tcg_gen_addi_tl(addr, addr, 8); + tcg_gen_qemu_st_i64(cpu_fpr[rd/2+1], addr, da.mem_idx, da.memop); + break; + default: + g_assert_not_reached(); + } + break; + default: { TCGv_i32 r_asi = tcg_const_i32(da.asi); -- 2.7.4