From: Peter Xu <peterx@redhat.com>
To: qemu-devel@nongnu.org
Cc: imammedo@redhat.com, rth@twiddle.net, ehabkost@redhat.com,
jasowang@redhat.com, marcel@redhat.com, mst@redhat.com,
pbonzini@redhat.com, jan.kiszka@web.de, rkrcmar@redhat.com,
alex.williamson@redhat.com, wexu@redhat.com,
davidkiarie4@gmail.com, peterx@redhat.com
Subject: [Qemu-devel] [PATCH v12 18/27] ioapic: register IOMMU IEC notifier for ioapic
Date: Thu, 14 Jul 2016 13:56:27 +0800 [thread overview]
Message-ID: <1468475796-7397-19-git-send-email-peterx@redhat.com> (raw)
In-Reply-To: <1468475796-7397-1-git-send-email-peterx@redhat.com>
Let IOAPIC the first consumer of x86 IOMMU IEC invalidation
notifiers. This is only used for split irqchip case, when vIOMMU
receives IR invalidation requests, IOAPIC will be notified to update
kernel irq routes. For simplicity, we just update all IOAPIC routes,
even if the invalidated entries are not IOAPIC ones.
Since now we are creating IOMMUs using "-device" parameter, IOMMU
device will be created after IOAPIC. We need to do the registration
after machine done by leveraging machine_done notifier.
Signed-off-by: Peter Xu <peterx@redhat.com>
---
hw/intc/ioapic.c | 31 +++++++++++++++++++++++++++++++
include/hw/i386/ioapic_internal.h | 2 ++
2 files changed, 33 insertions(+)
diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c
index c4469e4..819585d 100644
--- a/hw/intc/ioapic.c
+++ b/hw/intc/ioapic.c
@@ -31,6 +31,7 @@
#include "sysemu/kvm.h"
#include "target-i386/cpu.h"
#include "hw/i386/apic-msidef.h"
+#include "hw/i386/x86-iommu.h"
//#define DEBUG_IOAPIC
@@ -198,6 +199,16 @@ static void ioapic_update_kvm_routes(IOAPICCommonState *s)
#endif
}
+#ifdef CONFIG_KVM
+static void ioapic_iec_notifier(void *private, bool global,
+ uint32_t index, uint32_t mask)
+{
+ IOAPICCommonState *s = (IOAPICCommonState *)private;
+ /* For simplicity, we just update all the routes */
+ ioapic_update_kvm_routes(s);
+}
+#endif
+
void ioapic_eoi_broadcast(int vector)
{
IOAPICCommonState *s;
@@ -354,6 +365,24 @@ static const MemoryRegionOps ioapic_io_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
+static void ioapic_machine_done_notify(Notifier *notifier, void *data)
+{
+#ifdef CONFIG_KVM
+ IOAPICCommonState *s = container_of(notifier, IOAPICCommonState,
+ machine_done);
+
+ if (kvm_irqchip_is_split()) {
+ X86IOMMUState *iommu = x86_iommu_get_default();
+ if (iommu) {
+ /* Register this IOAPIC with IOMMU IEC notifier, so that
+ * when there are IR invalidates, we can be notified to
+ * update kernel IR cache. */
+ x86_iommu_iec_register_notifier(iommu, ioapic_iec_notifier, s);
+ }
+ }
+#endif
+}
+
static void ioapic_realize(DeviceState *dev, Error **errp)
{
IOAPICCommonState *s = IOAPIC_COMMON(dev);
@@ -364,6 +393,8 @@ static void ioapic_realize(DeviceState *dev, Error **errp)
qdev_init_gpio_in(dev, ioapic_set_irq, IOAPIC_NUM_PINS);
ioapics[ioapic_no] = s;
+ s->machine_done.notify = ioapic_machine_done_notify;
+ qemu_add_machine_init_done_notifier(&s->machine_done);
}
static void ioapic_class_init(ObjectClass *klass, void *data)
diff --git a/include/hw/i386/ioapic_internal.h b/include/hw/i386/ioapic_internal.h
index 31dafb3..84e3deb 100644
--- a/include/hw/i386/ioapic_internal.h
+++ b/include/hw/i386/ioapic_internal.h
@@ -25,6 +25,7 @@
#include "hw/hw.h"
#include "exec/memory.h"
#include "hw/sysbus.h"
+#include "qemu/notify.h"
#define MAX_IOAPICS 1
@@ -107,6 +108,7 @@ struct IOAPICCommonState {
uint8_t ioregsel;
uint32_t irr;
uint64_t ioredtbl[IOAPIC_NUM_PINS];
+ Notifier machine_done;
};
void ioapic_reset_common(DeviceState *dev);
--
2.4.11
next prev parent reply other threads:[~2016-07-14 5:57 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-14 5:56 [Qemu-devel] [PATCH v12 00/27] IOMMU: Enable interrupt remapping for Intel IOMMU Peter Xu
2016-07-14 5:56 ` [Qemu-devel] [PATCH v12 01/27] x86-iommu: introduce parent class Peter Xu
2016-07-14 5:56 ` [Qemu-devel] [PATCH v12 02/27] intel_iommu: rename VTD_PCI_DEVFN_MAX to x86-iommu Peter Xu
2016-07-14 5:56 ` [Qemu-devel] [PATCH v12 03/27] x86-iommu: provide x86_iommu_get_default Peter Xu
2016-07-14 5:56 ` [Qemu-devel] [PATCH v12 04/27] x86-iommu: introduce "intremap" property Peter Xu
2016-07-14 5:56 ` [Qemu-devel] [PATCH v12 05/27] acpi: enable INTR for DMAR report structure Peter Xu
2016-07-14 5:56 ` [Qemu-devel] [PATCH v12 06/27] intel_iommu: allow queued invalidation for IR Peter Xu
2016-07-14 5:56 ` [Qemu-devel] [PATCH v12 07/27] intel_iommu: set IR bit for ECAP register Peter Xu
2016-07-14 5:56 ` [Qemu-devel] [PATCH v12 08/27] acpi: add DMAR scope definition for root IOAPIC Peter Xu
2016-07-14 5:56 ` [Qemu-devel] [PATCH v12 09/27] intel_iommu: define interrupt remap table addr register Peter Xu
2016-07-14 5:56 ` [Qemu-devel] [PATCH v12 10/27] intel_iommu: handle interrupt remap enable Peter Xu
2016-07-14 5:56 ` [Qemu-devel] [PATCH v12 11/27] intel_iommu: define several structs for IOMMU IR Peter Xu
2016-07-14 5:56 ` [Qemu-devel] [PATCH v12 12/27] intel_iommu: add IR translation faults defines Peter Xu
2016-07-14 5:56 ` [Qemu-devel] [PATCH v12 13/27] intel_iommu: Add support for PCI MSI remap Peter Xu
2016-07-21 17:45 ` Michael S. Tsirkin
2016-07-22 3:17 ` Peter Xu
2016-07-14 5:56 ` [Qemu-devel] [PATCH v12 14/27] q35: ioapic: add support for emulated IOAPIC IR Peter Xu
2016-07-14 5:56 ` [Qemu-devel] [PATCH v12 15/27] ioapic: introduce ioapic_entry_parse() helper Peter Xu
2016-07-14 5:56 ` [Qemu-devel] [PATCH v12 16/27] intel_iommu: add support for split irqchip Peter Xu
2016-07-14 5:56 ` [Qemu-devel] [PATCH v12 17/27] x86-iommu: introduce IEC notifiers Peter Xu
2016-07-14 5:56 ` Peter Xu [this message]
2016-07-14 5:56 ` [Qemu-devel] [PATCH v12 19/27] intel_iommu: Add support for Extended Interrupt Mode Peter Xu
2016-07-14 5:56 ` [Qemu-devel] [PATCH v12 20/27] intel_iommu: add SID validation for IR Peter Xu
2016-07-14 5:56 ` [Qemu-devel] [PATCH v12 21/27] kvm-irqchip: simplify kvm_irqchip_add_msi_route Peter Xu
2016-07-14 5:56 ` [Qemu-devel] [PATCH v12 22/27] kvm-irqchip: i386: add hook for add/remove virq Peter Xu
2016-07-14 5:56 ` [Qemu-devel] [PATCH v12 23/27] kvm-irqchip: x86: add msi route notify fn Peter Xu
2016-07-14 5:56 ` [Qemu-devel] [PATCH v12 24/27] kvm-irqchip: do explicit commit when update irq Peter Xu
2016-07-14 5:56 ` [Qemu-devel] [PATCH v12 25/27] intel_iommu: support all masks in interrupt entry cache invalidation Peter Xu
2016-07-14 5:56 ` [Qemu-devel] [PATCH v12 26/27] kvm-all: add trace events for kvm irqchip ops Peter Xu
2016-07-14 5:56 ` [Qemu-devel] [PATCH v12 27/27] intel_iommu: disallow kernel-irqchip=on with IR Peter Xu
2016-09-22 8:29 ` [Qemu-devel] [PATCH v12 00/27] IOMMU: Enable interrupt remapping for Intel IOMMU Igor Mammedov
2016-09-22 9:08 ` Peter Xu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1468475796-7397-19-git-send-email-peterx@redhat.com \
--to=peterx@redhat.com \
--cc=alex.williamson@redhat.com \
--cc=davidkiarie4@gmail.com \
--cc=ehabkost@redhat.com \
--cc=imammedo@redhat.com \
--cc=jan.kiszka@web.de \
--cc=jasowang@redhat.com \
--cc=marcel@redhat.com \
--cc=mst@redhat.com \
--cc=pbonzini@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=rkrcmar@redhat.com \
--cc=rth@twiddle.net \
--cc=wexu@redhat.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).