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From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au
Cc: qemu-devel@nongnu.org, aneesh.kumar@linux.vnet.ibm.com,
	benh@kernel.crashing.org, nikunj@linux.vnet.ibm.com
Subject: [Qemu-devel] [RFC v1 08/13] target-ppc: add cnttzw[.] instruction
Date: Mon, 18 Jul 2016 22:35:12 +0530	[thread overview]
Message-ID: <1468861517-2508-9-git-send-email-nikunj@linux.vnet.ibm.com> (raw)
In-Reply-To: <1468861517-2508-1-git-send-email-nikunj@linux.vnet.ibm.com>

Add ISA3.0: Count trailing zeros word instruction.

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
 target-ppc/helper.h     |  1 +
 target-ppc/int_helper.c |  5 +++++
 target-ppc/translate.c  | 10 ++++++++++
 3 files changed, 16 insertions(+)

diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 0c29c01..9c79808 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -38,6 +38,7 @@ DEF_HELPER_4(divweu, tl, env, tl, tl, i32)
 DEF_HELPER_4(divwe, tl, env, tl, tl, i32)
 
 DEF_HELPER_FLAGS_1(cntlzw, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(cnttzw, TCG_CALL_NO_RWG_SE, tl, tl)
 DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl)
 DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
 DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 93e8dfa..02b6df3 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -145,6 +145,11 @@ target_ulong helper_cntlzw(target_ulong t)
     return clz32(t);
 }
 
+target_ulong helper_cnttzw(target_ulong t)
+{
+    return ctz32(t);
+}
+
 #if defined(TARGET_PPC64)
 target_ulong helper_cntlzd(target_ulong t)
 {
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 5f38080..a57f7dd 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1580,6 +1580,15 @@ static void gen_cntlzw(DisasContext *ctx)
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
 }
+
+/* cnttzw */
+static void gen_cnttzw(DisasContext *ctx)
+{
+    gen_helper_cnttzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
+    if (unlikely(Rc(ctx->opcode) != 0))
+        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
+}
+
 /* eqv & eqv. */
 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
 /* extsb & extsb. */
@@ -10053,6 +10062,7 @@ GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
+GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
-- 
2.7.4

  parent reply	other threads:[~2016-07-18 17:05 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-07-18 17:05 [Qemu-devel] [RFC v1 00/13] POWER9 TCG enablements - part1 Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 01/13] target-ppc: Introduce Power9 family Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 02/13] target-ppc: Introduce POWER ISA 3.0 flag Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 03/13] target-ppc: adding addpcis instruction Nikunj A Dadhania
2016-07-21  7:53   ` Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 04/13] target-ppc: add cmprb instruction Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 05/13] target-ppc: add modulo word operations Nikunj A Dadhania
2016-07-22  4:51   ` David Gibson
2016-07-22  5:29     ` Nikunj A Dadhania
2016-07-22  6:09       ` David Gibson
2016-07-22  6:54         ` Nikunj A Dadhania
2016-07-22  7:12           ` David Gibson
2016-07-22  8:00             ` Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 06/13] target-ppc: add modulo dword operations Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 07/13] target-ppc: add cnttzd[.] instruction Nikunj A Dadhania
2016-07-21  6:28   ` Richard Henderson
2016-07-21  7:54     ` Nikunj A Dadhania
2016-07-18 17:05 ` Nikunj A Dadhania [this message]
2016-07-21  6:29   ` [Qemu-devel] [RFC v1 08/13] target-ppc: add cnttzw[.] instruction Richard Henderson
2016-07-21  7:54     ` Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 09/13] target-ppc: add cmpeqb instruction Nikunj A Dadhania
2016-07-18 17:12   ` Nikunj A Dadhania
2016-07-21  6:41   ` Richard Henderson
2016-07-21  8:02     ` Nikunj A Dadhania
2016-07-22 19:28     ` Nikunj A Dadhania
2016-07-23  1:17       ` Richard Henderson
2016-07-23  6:08         ` Nikunj A Dadhania
2016-07-23 16:01           ` Richard Henderson
2016-07-22  4:57   ` David Gibson
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 10/13] target-ppc: add setb instruction Nikunj A Dadhania
2016-07-21  6:49   ` Richard Henderson
2016-07-22  4:59   ` David Gibson
2016-07-22  5:30     ` Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 11/13] target-ppc: add maddld instruction Nikunj A Dadhania
2016-07-21  6:54   ` Richard Henderson
2016-07-21  6:59     ` Richard Henderson
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 12/13] target-ppc: add maddhd and maddhdu instruction Nikunj A Dadhania
2016-07-21  7:02   ` Richard Henderson
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 13/13] target-ppc: introduce opc4 for Expanded Opcode Nikunj A Dadhania
2016-07-22  5:07   ` David Gibson
2016-07-22  5:35     ` Nikunj A Dadhania
2016-07-22  6:08       ` David Gibson
2016-07-22  6:58         ` Nikunj A Dadhania
2016-07-22  9:49   ` Bharata B Rao
2016-07-22 10:00     ` Nikunj A Dadhania

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