* [Qemu-devel] [PATCH v3 01/10] Avoid needless calls to address_space_rw()
2016-07-20 5:02 [Qemu-devel] [PATCH v3 00/10] Support non-direct memory writes in cpu_memory_rw_debug Andrey Smirnov
@ 2016-07-20 5:02 ` Andrey Smirnov
2016-07-20 5:02 ` [Qemu-devel] [PATCH v3 02/10] Change signature of address_space_read() to avoid casting Andrey Smirnov
` (8 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Andrey Smirnov @ 2016-07-20 5:02 UTC (permalink / raw)
To: qemu-devel
Cc: Andrey Smirnov, Peter Maydell, David Gibson, qemu-ppc, qemu-arm,
kvm
Avoid calling address_space_rw() when direction of the transfer is
constant and known at compile time and replace them with explicit calls
to address_space_read()/address_space_write().
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
dma-helpers.c | 4 ++--
exec.c | 10 +++++-----
hw/net/dp8393x.c | 58 +++++++++++++++++++++++++++++---------------------------
3 files changed, 37 insertions(+), 35 deletions(-)
diff --git a/dma-helpers.c b/dma-helpers.c
index 9defc10..98c070e 100644
--- a/dma-helpers.c
+++ b/dma-helpers.c
@@ -28,8 +28,8 @@ int dma_memory_set(AddressSpace *as, dma_addr_t addr, uint8_t c, dma_addr_t len)
memset(fillbuf, c, FILLBUF_SIZE);
while (len > 0) {
l = len < FILLBUF_SIZE ? len : FILLBUF_SIZE;
- error |= address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED,
- fillbuf, l, true);
+ error |= address_space_write(as, addr, MEMTXATTRS_UNSPECIFIED,
+ fillbuf, l);
len -= l;
addr += l;
}
diff --git a/exec.c b/exec.c
index 011babd..337ec01 100644
--- a/exec.c
+++ b/exec.c
@@ -3224,7 +3224,7 @@ uint32_t address_space_ldub(AddressSpace *as, hwaddr addr,
uint8_t val;
MemTxResult r;
- r = address_space_rw(as, addr, attrs, &val, 1, 0);
+ r = address_space_read(as, addr, attrs, &val, 1);
if (result) {
*result = r;
}
@@ -3474,7 +3474,7 @@ void address_space_stb(AddressSpace *as, hwaddr addr, uint32_t val,
uint8_t v = val;
MemTxResult r;
- r = address_space_rw(as, addr, attrs, &v, 1, 1);
+ r = address_space_write(as, addr, attrs, &v, 1);
if (result) {
*result = r;
}
@@ -3582,7 +3582,7 @@ void address_space_stq(AddressSpace *as, hwaddr addr, uint64_t val,
{
MemTxResult r;
val = tswap64(val);
- r = address_space_rw(as, addr, attrs, (void *) &val, 8, 1);
+ r = address_space_write(as, addr, attrs, (void *) &val, 8);
if (result) {
*result = r;
}
@@ -3593,7 +3593,7 @@ void address_space_stq_le(AddressSpace *as, hwaddr addr, uint64_t val,
{
MemTxResult r;
val = cpu_to_le64(val);
- r = address_space_rw(as, addr, attrs, (void *) &val, 8, 1);
+ r = address_space_write(as, addr, attrs, (void *) &val, 8);
if (result) {
*result = r;
}
@@ -3603,7 +3603,7 @@ void address_space_stq_be(AddressSpace *as, hwaddr addr, uint64_t val,
{
MemTxResult r;
val = cpu_to_be64(val);
- r = address_space_rw(as, addr, attrs, (void *) &val, 8, 1);
+ r = address_space_write(as, addr, attrs, (void *) &val, 8);
if (result) {
*result = r;
}
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
index 0fa652c..3af044f 100644
--- a/hw/net/dp8393x.c
+++ b/hw/net/dp8393x.c
@@ -203,9 +203,9 @@ static void dp8393x_do_load_cam(dp8393xState *s)
while (s->regs[SONIC_CDC] & 0x1f) {
/* Fill current entry */
- address_space_rw(&s->as,
+ address_space_read(&s->as,
(s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP],
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
+ MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size);
s->cam[index][0] = data[1 * width] & 0xff;
s->cam[index][1] = data[1 * width] >> 8;
s->cam[index][2] = data[2 * width] & 0xff;
@@ -222,9 +222,9 @@ static void dp8393x_do_load_cam(dp8393xState *s)
}
/* Read CAM enable */
- address_space_rw(&s->as,
+ address_space_read(&s->as,
(s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP],
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
+ MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size);
s->regs[SONIC_CE] = data[0 * width];
DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]);
@@ -242,9 +242,9 @@ static void dp8393x_do_read_rra(dp8393xState *s)
/* Read memory */
width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
size = sizeof(uint16_t) * 4 * width;
- address_space_rw(&s->as,
+ address_space_read(&s->as,
(s->regs[SONIC_URRA] << 16) | s->regs[SONIC_RRP],
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
+ MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size);
/* Update SONIC registers */
s->regs[SONIC_CRBA0] = data[0 * width];
@@ -360,9 +360,9 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
(s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_CTDA]);
size = sizeof(uint16_t) * 6 * width;
s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA];
- address_space_rw(&s->as,
+ address_space_read(&s->as,
((s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA]) + sizeof(uint16_t) * width,
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
+ MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size);
tx_len = 0;
/* Update registers */
@@ -386,18 +386,18 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
if (tx_len + len > sizeof(s->tx_buffer)) {
len = sizeof(s->tx_buffer) - tx_len;
}
- address_space_rw(&s->as,
+ address_space_read(&s->as,
(s->regs[SONIC_TSA1] << 16) | s->regs[SONIC_TSA0],
- MEMTXATTRS_UNSPECIFIED, &s->tx_buffer[tx_len], len, 0);
+ MEMTXATTRS_UNSPECIFIED, &s->tx_buffer[tx_len], len);
tx_len += len;
i++;
if (i != s->regs[SONIC_TFC]) {
/* Read next fragment details */
size = sizeof(uint16_t) * 3 * width;
- address_space_rw(&s->as,
+ address_space_read(&s->as,
((s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA]) + sizeof(uint16_t) * (4 + 3 * i) * width,
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
+ MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size);
s->regs[SONIC_TSA0] = data[0 * width];
s->regs[SONIC_TSA1] = data[1 * width];
s->regs[SONIC_TFS] = data[2 * width];
@@ -429,16 +429,16 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
/* Write status */
data[0 * width] = s->regs[SONIC_TCR] & 0x0fff; /* status */
size = sizeof(uint16_t) * width;
- address_space_rw(&s->as,
+ address_space_write(&s->as,
(s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA],
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1);
+ MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size);
if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) {
/* Read footer of packet */
size = sizeof(uint16_t) * width;
- address_space_rw(&s->as,
+ address_space_read(&s->as,
((s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA]) + sizeof(uint16_t) * (4 + 3 * s->regs[SONIC_TFC]) * width,
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
+ MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size);
s->regs[SONIC_CTDA] = data[0 * width] & ~0x1;
if (data[0 * width] & 0x1) {
/* EOL detected */
@@ -701,8 +701,8 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
/* Are we still in resource exhaustion? */
size = sizeof(uint16_t) * 1 * width;
address = ((s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]) + sizeof(uint16_t) * 5 * width;
- address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
- (uint8_t *)data, size, 0);
+ address_space_read(&s->as, address, MEMTXATTRS_UNSPECIFIED,
+ (uint8_t *)data, size);
if (data[0 * width] & 0x1) {
/* Still EOL ; stop reception */
return -1;
@@ -721,11 +721,11 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
/* Put packet into RBA */
DPRINTF("Receive packet at %08x\n", (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0]);
address = (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0];
- address_space_rw(&s->as, address,
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)buf, rx_len, 1);
+ address_space_write(&s->as, address,
+ MEMTXATTRS_UNSPECIFIED, (uint8_t *)buf, rx_len);
address += rx_len;
- address_space_rw(&s->as, address,
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)&checksum, 4, 1);
+ address_space_write(&s->as, address,
+ MEMTXATTRS_UNSPECIFIED, (uint8_t *)&checksum, 4);
rx_len += 4;
s->regs[SONIC_CRBA1] = address >> 16;
s->regs[SONIC_CRBA0] = address & 0xffff;
@@ -753,23 +753,25 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
data[3 * width] = s->regs[SONIC_TRBA1]; /* pkt_ptr1 */
data[4 * width] = s->regs[SONIC_RSC]; /* seq_no */
size = sizeof(uint16_t) * 5 * width;
- address_space_rw(&s->as, (s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA],
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1);
+ address_space_write(&s->as,
+ (s->regs[SONIC_URDA] << 16) |
+ s->regs[SONIC_CRDA],
+ MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size);
/* Move to next descriptor */
size = sizeof(uint16_t) * width;
- address_space_rw(&s->as,
+ address_space_read(&s->as,
((s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]) + sizeof(uint16_t) * 5 * width,
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
+ MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size);
s->regs[SONIC_LLFA] = data[0 * width];
if (s->regs[SONIC_LLFA] & 0x1) {
/* EOL detected */
s->regs[SONIC_ISR] |= SONIC_ISR_RDE;
} else {
data[0 * width] = 0; /* in_use */
- address_space_rw(&s->as,
+ address_space_write(&s->as,
((s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]) + sizeof(uint16_t) * 6 * width,
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, sizeof(uint16_t), 1);
+ MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, sizeof(uint16_t));
s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff);
--
2.5.5
^ permalink raw reply related [flat|nested] 15+ messages in thread* [Qemu-devel] [PATCH v3 02/10] Change signature of address_space_read() to avoid casting
2016-07-20 5:02 [Qemu-devel] [PATCH v3 00/10] Support non-direct memory writes in cpu_memory_rw_debug Andrey Smirnov
2016-07-20 5:02 ` [Qemu-devel] [PATCH v3 01/10] Avoid needless calls to address_space_rw() Andrey Smirnov
@ 2016-07-20 5:02 ` Andrey Smirnov
2016-07-20 5:02 ` [Qemu-devel] [PATCH v3 03/10] Change signature of address_space_write() " Andrey Smirnov
` (7 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Andrey Smirnov @ 2016-07-20 5:02 UTC (permalink / raw)
To: qemu-devel
Cc: Andrey Smirnov, Peter Maydell, David Gibson, qemu-ppc, qemu-arm,
kvm
Change signature of address_space_read() to expectet void * as a buffer
instead of uint8_t * to avoid forcing the caller of the function to do a
type cast.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
exec.c | 2 +-
hw/net/dp8393x.c | 16 ++++++++--------
hw/virtio/virtio.c | 2 +-
include/exec/memory.h | 2 +-
4 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/exec.c b/exec.c
index 337ec01..76d55ed 100644
--- a/exec.c
+++ b/exec.c
@@ -2736,7 +2736,7 @@ MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
if (is_write) {
return address_space_write(as, addr, attrs, (uint8_t *)buf, len);
} else {
- return address_space_read(as, addr, attrs, (uint8_t *)buf, len);
+ return address_space_read(as, addr, attrs, buf, len);
}
}
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
index 3af044f..b8b33ee 100644
--- a/hw/net/dp8393x.c
+++ b/hw/net/dp8393x.c
@@ -205,7 +205,7 @@ static void dp8393x_do_load_cam(dp8393xState *s)
/* Fill current entry */
address_space_read(&s->as,
(s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP],
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size);
+ MEMTXATTRS_UNSPECIFIED, data, size);
s->cam[index][0] = data[1 * width] & 0xff;
s->cam[index][1] = data[1 * width] >> 8;
s->cam[index][2] = data[2 * width] & 0xff;
@@ -224,7 +224,7 @@ static void dp8393x_do_load_cam(dp8393xState *s)
/* Read CAM enable */
address_space_read(&s->as,
(s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP],
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size);
+ MEMTXATTRS_UNSPECIFIED, data, size);
s->regs[SONIC_CE] = data[0 * width];
DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]);
@@ -244,7 +244,7 @@ static void dp8393x_do_read_rra(dp8393xState *s)
size = sizeof(uint16_t) * 4 * width;
address_space_read(&s->as,
(s->regs[SONIC_URRA] << 16) | s->regs[SONIC_RRP],
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size);
+ MEMTXATTRS_UNSPECIFIED, data, size);
/* Update SONIC registers */
s->regs[SONIC_CRBA0] = data[0 * width];
@@ -362,7 +362,7 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA];
address_space_read(&s->as,
((s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA]) + sizeof(uint16_t) * width,
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size);
+ MEMTXATTRS_UNSPECIFIED, data, size);
tx_len = 0;
/* Update registers */
@@ -397,7 +397,7 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
size = sizeof(uint16_t) * 3 * width;
address_space_read(&s->as,
((s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA]) + sizeof(uint16_t) * (4 + 3 * i) * width,
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size);
+ MEMTXATTRS_UNSPECIFIED, data, size);
s->regs[SONIC_TSA0] = data[0 * width];
s->regs[SONIC_TSA1] = data[1 * width];
s->regs[SONIC_TFS] = data[2 * width];
@@ -438,7 +438,7 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
size = sizeof(uint16_t) * width;
address_space_read(&s->as,
((s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA]) + sizeof(uint16_t) * (4 + 3 * s->regs[SONIC_TFC]) * width,
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size);
+ MEMTXATTRS_UNSPECIFIED, data, size);
s->regs[SONIC_CTDA] = data[0 * width] & ~0x1;
if (data[0 * width] & 0x1) {
/* EOL detected */
@@ -702,7 +702,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
size = sizeof(uint16_t) * 1 * width;
address = ((s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]) + sizeof(uint16_t) * 5 * width;
address_space_read(&s->as, address, MEMTXATTRS_UNSPECIFIED,
- (uint8_t *)data, size);
+ data, size);
if (data[0 * width] & 0x1) {
/* Still EOL ; stop reception */
return -1;
@@ -762,7 +762,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
size = sizeof(uint16_t) * width;
address_space_read(&s->as,
((s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]) + sizeof(uint16_t) * 5 * width,
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size);
+ MEMTXATTRS_UNSPECIFIED, data, size);
s->regs[SONIC_LLFA] = data[0 * width];
if (s->regs[SONIC_LLFA] & 0x1) {
/* EOL detected */
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 18153d5..6e04cea 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -122,7 +122,7 @@ static void vring_desc_read(VirtIODevice *vdev, VRingDesc *desc,
hwaddr desc_pa, int i)
{
address_space_read(&address_space_memory, desc_pa + i * sizeof(VRingDesc),
- MEMTXATTRS_UNSPECIFIED, (void *)desc, sizeof(VRingDesc));
+ MEMTXATTRS_UNSPECIFIED, desc, sizeof(VRingDesc));
virtio_tswap64s(vdev, &desc->addr);
virtio_tswap32s(vdev, &desc->len);
virtio_tswap16s(vdev, &desc->flags);
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 3e4d416..262ecab 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -1451,7 +1451,7 @@ static inline bool memory_access_is_direct(MemoryRegion *mr, bool is_write)
*/
static inline __attribute__((__always_inline__))
MemTxResult address_space_read(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
- uint8_t *buf, int len)
+ void *buf, int len)
{
MemTxResult result = MEMTX_OK;
hwaddr l, addr1;
--
2.5.5
^ permalink raw reply related [flat|nested] 15+ messages in thread* [Qemu-devel] [PATCH v3 03/10] Change signature of address_space_write() to avoid casting
2016-07-20 5:02 [Qemu-devel] [PATCH v3 00/10] Support non-direct memory writes in cpu_memory_rw_debug Andrey Smirnov
2016-07-20 5:02 ` [Qemu-devel] [PATCH v3 01/10] Avoid needless calls to address_space_rw() Andrey Smirnov
2016-07-20 5:02 ` [Qemu-devel] [PATCH v3 02/10] Change signature of address_space_read() to avoid casting Andrey Smirnov
@ 2016-07-20 5:02 ` Andrey Smirnov
2016-07-20 5:02 ` [Qemu-devel] [PATCH v3 04/10] address_space_write_continue: Distill common code Andrey Smirnov
` (6 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Andrey Smirnov @ 2016-07-20 5:02 UTC (permalink / raw)
To: qemu-devel
Cc: Andrey Smirnov, Peter Maydell, David Gibson, qemu-ppc, qemu-arm,
kvm
Change signature of address_space_write() to expectet void * as a buffer
instead of uint8_t * to avoid forcing the caller of the function to do a
type cast.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
exec.c | 10 +++++-----
hw/net/dp8393x.c | 10 +++++-----
hw/virtio/virtio.c | 2 +-
include/exec/memory.h | 2 +-
4 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/exec.c b/exec.c
index 76d55ed..44cd424 100644
--- a/exec.c
+++ b/exec.c
@@ -2621,7 +2621,7 @@ static MemTxResult address_space_write_continue(AddressSpace *as, hwaddr addr,
}
MemTxResult address_space_write(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
- const uint8_t *buf, int len)
+ const void *buf, int len)
{
hwaddr l;
hwaddr addr1;
@@ -2734,7 +2734,7 @@ MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
uint8_t *buf, int len, bool is_write)
{
if (is_write) {
- return address_space_write(as, addr, attrs, (uint8_t *)buf, len);
+ return address_space_write(as, addr, attrs, buf, len);
} else {
return address_space_read(as, addr, attrs, buf, len);
}
@@ -3582,7 +3582,7 @@ void address_space_stq(AddressSpace *as, hwaddr addr, uint64_t val,
{
MemTxResult r;
val = tswap64(val);
- r = address_space_write(as, addr, attrs, (void *) &val, 8);
+ r = address_space_write(as, addr, attrs, &val, 8);
if (result) {
*result = r;
}
@@ -3593,7 +3593,7 @@ void address_space_stq_le(AddressSpace *as, hwaddr addr, uint64_t val,
{
MemTxResult r;
val = cpu_to_le64(val);
- r = address_space_write(as, addr, attrs, (void *) &val, 8);
+ r = address_space_write(as, addr, attrs, &val, 8);
if (result) {
*result = r;
}
@@ -3603,7 +3603,7 @@ void address_space_stq_be(AddressSpace *as, hwaddr addr, uint64_t val,
{
MemTxResult r;
val = cpu_to_be64(val);
- r = address_space_write(as, addr, attrs, (void *) &val, 8);
+ r = address_space_write(as, addr, attrs, &val, 8);
if (result) {
*result = r;
}
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
index b8b33ee..e5712a2 100644
--- a/hw/net/dp8393x.c
+++ b/hw/net/dp8393x.c
@@ -431,7 +431,7 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
size = sizeof(uint16_t) * width;
address_space_write(&s->as,
(s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA],
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size);
+ MEMTXATTRS_UNSPECIFIED, data, size);
if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) {
/* Read footer of packet */
@@ -722,10 +722,10 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
DPRINTF("Receive packet at %08x\n", (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0]);
address = (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0];
address_space_write(&s->as, address,
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)buf, rx_len);
+ MEMTXATTRS_UNSPECIFIED, buf, rx_len);
address += rx_len;
address_space_write(&s->as, address,
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)&checksum, 4);
+ MEMTXATTRS_UNSPECIFIED, &checksum, 4);
rx_len += 4;
s->regs[SONIC_CRBA1] = address >> 16;
s->regs[SONIC_CRBA0] = address & 0xffff;
@@ -756,7 +756,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
address_space_write(&s->as,
(s->regs[SONIC_URDA] << 16) |
s->regs[SONIC_CRDA],
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size);
+ MEMTXATTRS_UNSPECIFIED, data, size);
/* Move to next descriptor */
size = sizeof(uint16_t) * width;
@@ -771,7 +771,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
data[0 * width] = 0; /* in_use */
address_space_write(&s->as,
((s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]) + sizeof(uint16_t) * 6 * width,
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, sizeof(uint16_t));
+ MEMTXATTRS_UNSPECIFIED, data, sizeof(uint16_t));
s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff);
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 6e04cea..f4b7d59 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -164,7 +164,7 @@ static inline void vring_used_write(VirtQueue *vq, VRingUsedElem *uelem,
virtio_tswap32s(vq->vdev, &uelem->len);
pa = vq->vring.used + offsetof(VRingUsed, ring[i]);
address_space_write(&address_space_memory, pa, MEMTXATTRS_UNSPECIFIED,
- (void *)uelem, sizeof(VRingUsedElem));
+ uelem, sizeof(VRingUsedElem));
}
static uint16_t vring_used_idx(VirtQueue *vq)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 262ecab..7851ca9 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -1304,7 +1304,7 @@ MemTxResult address_space_rw(AddressSpace *as, hwaddr addr,
*/
MemTxResult address_space_write(AddressSpace *as, hwaddr addr,
MemTxAttrs attrs,
- const uint8_t *buf, int len);
+ const void *buf, int len);
/* address_space_ld*: load from an address space
* address_space_st*: store to an address space
--
2.5.5
^ permalink raw reply related [flat|nested] 15+ messages in thread* [Qemu-devel] [PATCH v3 04/10] address_space_write_continue: Distill common code
2016-07-20 5:02 [Qemu-devel] [PATCH v3 00/10] Support non-direct memory writes in cpu_memory_rw_debug Andrey Smirnov
` (2 preceding siblings ...)
2016-07-20 5:02 ` [Qemu-devel] [PATCH v3 03/10] Change signature of address_space_write() " Andrey Smirnov
@ 2016-07-20 5:02 ` Andrey Smirnov
2016-07-20 5:02 ` [Qemu-devel] [PATCH v3 05/10] Rename MMUAccessType to MemoryAccessType Andrey Smirnov
` (5 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Andrey Smirnov @ 2016-07-20 5:02 UTC (permalink / raw)
To: qemu-devel
Cc: Andrey Smirnov, Peter Maydell, David Gibson, qemu-ppc, qemu-arm,
kvm
Move call to memory_region_dispatch_write() outside of swtich statement
since the only thing that is different about all of those call is
"length" argument and that matches value in "l".
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
exec.c | 23 +++++++----------------
1 file changed, 7 insertions(+), 16 deletions(-)
diff --git a/exec.c b/exec.c
index 44cd424..e2425c5 100644
--- a/exec.c
+++ b/exec.c
@@ -2567,32 +2567,23 @@ static MemTxResult address_space_write_continue(AddressSpace *as, hwaddr addr,
potential bugs */
switch (l) {
case 8:
- /* 64 bit write access */
- val = ldq_p(buf);
- result |= memory_region_dispatch_write(mr, addr1, val, 8,
- attrs);
+ val = ldq_p(buf); /* 64 bit write access */
break;
case 4:
- /* 32 bit write access */
- val = ldl_p(buf);
- result |= memory_region_dispatch_write(mr, addr1, val, 4,
- attrs);
+ val = ldl_p(buf); /* 32 bit write access */
break;
case 2:
- /* 16 bit write access */
- val = lduw_p(buf);
- result |= memory_region_dispatch_write(mr, addr1, val, 2,
- attrs);
+ val = lduw_p(buf); /* 16 bit write access */
break;
case 1:
- /* 8 bit write access */
- val = ldub_p(buf);
- result |= memory_region_dispatch_write(mr, addr1, val, 1,
- attrs);
+ val = ldub_p(buf); /* 8 bit write access */
break;
default:
abort();
}
+
+ result |= memory_region_dispatch_write(mr, addr1, val, l,
+ attrs);
} else {
/* RAM case */
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
--
2.5.5
^ permalink raw reply related [flat|nested] 15+ messages in thread* [Qemu-devel] [PATCH v3 05/10] Rename MMUAccessType to MemoryAccessType
2016-07-20 5:02 [Qemu-devel] [PATCH v3 00/10] Support non-direct memory writes in cpu_memory_rw_debug Andrey Smirnov
` (3 preceding siblings ...)
2016-07-20 5:02 ` [Qemu-devel] [PATCH v3 04/10] address_space_write_continue: Distill common code Andrey Smirnov
@ 2016-07-20 5:02 ` Andrey Smirnov
2016-07-20 9:34 ` David Gibson
2016-07-20 5:02 ` [Qemu-devel] [PATCH v3 06/10] Change signature of cpu_memory_rw_debug() to avoid casting Andrey Smirnov
` (4 subsequent siblings)
9 siblings, 1 reply; 15+ messages in thread
From: Andrey Smirnov @ 2016-07-20 5:02 UTC (permalink / raw)
To: qemu-devel
Cc: Andrey Smirnov, Peter Maydell, David Gibson, qemu-ppc, qemu-arm,
kvm
Rename MMUAccessType to MemoryAccessType and MMU_*
constants to corresponding MEM_* constants, so it would be possible to
re-use these defenitions in other, non MMU-related, contexts.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
include/exec/exec-all.h | 2 +-
include/qom/cpu.h | 14 +++++++-------
softmmu_template.h | 18 +++++++++---------
target-alpha/cpu.h | 2 +-
target-alpha/mem_helper.c | 4 ++--
target-arm/internals.h | 2 +-
target-arm/op_helper.c | 14 +++++++-------
target-cris/op_helper.c | 2 +-
target-i386/mem_helper.c | 2 +-
target-lm32/op_helper.c | 2 +-
target-m68k/op_helper.c | 2 +-
target-microblaze/op_helper.c | 2 +-
target-mips/cpu.h | 2 +-
target-mips/helper.c | 14 +++++++-------
target-mips/op_helper.c | 8 ++++----
target-moxie/helper.c | 2 +-
target-openrisc/mmu_helper.c | 2 +-
target-ppc/mmu_helper.c | 2 +-
target-s390x/helper.c | 2 +-
target-s390x/mem_helper.c | 8 ++++----
target-s390x/mmu_helper.c | 10 +++++-----
target-sh4/op_helper.c | 2 +-
target-sparc/cpu.h | 2 +-
target-sparc/ldst_helper.c | 4 ++--
target-tricore/op_helper.c | 2 +-
target-unicore32/op_helper.c | 2 +-
target-xtensa/cpu.h | 2 +-
target-xtensa/op_helper.c | 4 ++--
28 files changed, 67 insertions(+), 67 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index acda7b6..1d5c71e 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -361,7 +361,7 @@ extern uintptr_t tci_tb_ptr;
struct MemoryRegion *iotlb_to_region(CPUState *cpu,
hwaddr index, MemTxAttrs attrs);
-void tlb_fill(CPUState *cpu, target_ulong addr, MMUAccessType access_type,
+void tlb_fill(CPUState *cpu, target_ulong addr, MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr);
#endif
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index a6c6ed8..b23b4b1 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -60,11 +60,11 @@ typedef uint64_t vaddr;
#define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU)
#define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU)
-typedef enum MMUAccessType {
- MMU_DATA_LOAD = 0,
- MMU_DATA_STORE = 1,
- MMU_INST_FETCH = 2
-} MMUAccessType;
+typedef enum MemoryAccessType {
+ MEM_DATA_LOAD = 0,
+ MEM_DATA_STORE = 1,
+ MEM_INST_FETCH = 2
+} MemoryAccessType;
typedef struct CPUWatchpoint CPUWatchpoint;
@@ -148,7 +148,7 @@ typedef struct CPUClass {
void (*do_interrupt)(CPUState *cpu);
CPUUnassignedAccess do_unassigned_access;
void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
- MMUAccessType access_type,
+ MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr);
bool (*virtio_is_big_endian)(CPUState *cpu);
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
@@ -723,7 +723,7 @@ static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr,
}
static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
- MMUAccessType access_type,
+ MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
diff --git a/softmmu_template.h b/softmmu_template.h
index 284ab2c..e872a21 100644
--- a/softmmu_template.h
+++ b/softmmu_template.h
@@ -67,10 +67,10 @@
#endif
#ifdef SOFTMMU_CODE_ACCESS
-#define READ_ACCESS_TYPE MMU_INST_FETCH
+#define READ_ACCESS_TYPE MEM_INST_FETCH
#define ADDR_READ addr_code
#else
-#define READ_ACCESS_TYPE MMU_DATA_LOAD
+#define READ_ACCESS_TYPE MEM_DATA_LOAD
#define ADDR_READ addr_read
#endif
@@ -338,7 +338,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
retaddr -= GETPC_ADJ;
if (a_bits > 0 && (addr & ((1 << a_bits) - 1)) != 0) {
- cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
+ cpu_unaligned_access(ENV_GET_CPU(env), addr, MEM_DATA_STORE,
mmu_idx, retaddr);
}
@@ -346,7 +346,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
if ((addr & TARGET_PAGE_MASK)
!= (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
if (!VICTIM_TLB_HIT(addr_write, addr)) {
- tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
+ tlb_fill(ENV_GET_CPU(env), addr, MEM_DATA_STORE, mmu_idx, retaddr);
}
tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
}
@@ -381,7 +381,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
tlb_addr2 = env->tlb_table[mmu_idx][index2].addr_write;
if (page2 != (tlb_addr2 & (TARGET_PAGE_MASK | TLB_INVALID_MASK))
&& !VICTIM_TLB_HIT(addr_write, page2)) {
- tlb_fill(ENV_GET_CPU(env), page2, MMU_DATA_STORE,
+ tlb_fill(ENV_GET_CPU(env), page2, MEM_DATA_STORE,
mmu_idx, retaddr);
}
@@ -421,7 +421,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
retaddr -= GETPC_ADJ;
if (a_bits > 0 && (addr & ((1 << a_bits) - 1)) != 0) {
- cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
+ cpu_unaligned_access(ENV_GET_CPU(env), addr, MEM_DATA_STORE,
mmu_idx, retaddr);
}
@@ -429,7 +429,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
if ((addr & TARGET_PAGE_MASK)
!= (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
if (!VICTIM_TLB_HIT(addr_write, addr)) {
- tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
+ tlb_fill(ENV_GET_CPU(env), addr, MEM_DATA_STORE, mmu_idx, retaddr);
}
tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
}
@@ -464,7 +464,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
tlb_addr2 = env->tlb_table[mmu_idx][index2].addr_write;
if (page2 != (tlb_addr2 & (TARGET_PAGE_MASK | TLB_INVALID_MASK))
&& !VICTIM_TLB_HIT(addr_write, page2)) {
- tlb_fill(ENV_GET_CPU(env), page2, MMU_DATA_STORE,
+ tlb_fill(ENV_GET_CPU(env), page2, MEM_DATA_STORE,
mmu_idx, retaddr);
}
@@ -504,7 +504,7 @@ void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
!= (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
/* TLB entry is for a different page */
if (!VICTIM_TLB_HIT(addr_write, addr)) {
- tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
+ tlb_fill(ENV_GET_CPU(env), addr, MEM_DATA_STORE, mmu_idx, retaddr);
}
}
}
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index ac5e801..700f616 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -323,7 +323,7 @@ hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int alpha_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
- MMUAccessType access_type,
+ MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr);
#define cpu_list alpha_cpu_list
diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
index 1b2be50..d6ffabe 100644
--- a/target-alpha/mem_helper.c
+++ b/target-alpha/mem_helper.c
@@ -99,7 +99,7 @@ uint64_t helper_stq_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
}
void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
- MMUAccessType access_type,
+ MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
AlphaCPU *cpu = ALPHA_CPU(cs);
@@ -145,7 +145,7 @@ void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr,
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
-void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
+void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
int ret;
diff --git a/target-arm/internals.h b/target-arm/internals.h
index cd57401..d6fafc5 100644
--- a/target-arm/internals.h
+++ b/target-arm/internals.h
@@ -477,7 +477,7 @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
/* Raise a data fault alignment exception for the specified virtual address */
void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
- MMUAccessType access_type,
+ MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr);
/* Call the EL change hook if one has been registered */
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 3e8588e..74526a2 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -117,7 +117,7 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
* NULL, it means that the function was called in C code (i.e. not
* from generated code or from helper.c)
*/
-void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
+void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
bool ret;
@@ -149,14 +149,14 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
/* For insn and data aborts we assume there is no instruction syndrome
* information; this is always true for exceptions reported to EL1.
*/
- if (access_type == MMU_INST_FETCH) {
+ if (access_type == MEM_INST_FETCH) {
syn = syn_insn_abort(same_el, 0, fi.s1ptw, syn);
exc = EXCP_PREFETCH_ABORT;
} else {
syn = merge_syn_data_abort(env->exception.syndrome, target_el,
same_el, fi.s1ptw,
- access_type == MMU_DATA_STORE, syn);
- if (access_type == MMU_DATA_STORE
+ access_type == MEM_DATA_STORE, syn);
+ if (access_type == MEM_DATA_STORE
&& arm_feature(env, ARM_FEATURE_V6)) {
fsr |= (1 << 11);
}
@@ -171,7 +171,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
/* Raise a data fault alignment exception for the specified virtual address */
void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
- MMUAccessType access_type,
+ MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
ARMCPU *cpu = ARM_CPU(cs);
@@ -199,12 +199,12 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
env->exception.fsr = 0x1;
}
- if (access_type == MMU_DATA_STORE && arm_feature(env, ARM_FEATURE_V6)) {
+ if (access_type == MEM_DATA_STORE && arm_feature(env, ARM_FEATURE_V6)) {
env->exception.fsr |= (1 << 11);
}
syn = merge_syn_data_abort(env->exception.syndrome, target_el,
- same_el, 0, access_type == MMU_DATA_STORE,
+ same_el, 0, access_type == MEM_DATA_STORE,
0x21);
raise_exception(env, EXCP_DATA_ABORT, syn, target_el);
}
diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
index 5043039..c83e955 100644
--- a/target-cris/op_helper.c
+++ b/target-cris/op_helper.c
@@ -41,7 +41,7 @@
/* Try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
-void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
+void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
CRISCPU *cpu = CRIS_CPU(cs);
diff --git a/target-i386/mem_helper.c b/target-i386/mem_helper.c
index 5bc0594..679322c 100644
--- a/target-i386/mem_helper.c
+++ b/target-i386/mem_helper.c
@@ -140,7 +140,7 @@ void helper_boundl(CPUX86State *env, target_ulong a0, int v)
* from generated code or from helper.c)
*/
/* XXX: fix it to restore all registers */
-void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
+void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
int ret;
diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c
index 2177c8a..bc78f3c 100644
--- a/target-lm32/op_helper.c
+++ b/target-lm32/op_helper.c
@@ -144,7 +144,7 @@ uint32_t HELPER(rcsr_jrx)(CPULM32State *env)
* NULL, it means that the function was called in C code (i.e. not
* from generated code or from helper.c)
*/
-void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
+void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
int ret;
diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
index e41ae46..43f556e 100644
--- a/target-m68k/op_helper.c
+++ b/target-m68k/op_helper.c
@@ -39,7 +39,7 @@ static inline void do_interrupt_m68k_hardirq(CPUM68KState *env)
/* Try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
-void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
+void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
int ret;
diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
index 4a856e6..1e1690a 100644
--- a/target-microblaze/op_helper.c
+++ b/target-microblaze/op_helper.c
@@ -33,7 +33,7 @@
* NULL, it means that the function was called in C code (i.e. not
* from generated code or from helper.c)
*/
-void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
+void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
int ret;
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 5182dc7..55a3e34 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -657,7 +657,7 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
- MMUAccessType access_type,
+ MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr);
#if !defined(CONFIG_USER_ONLY)
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 9fbca26..bd3f7cd 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -88,13 +88,13 @@ int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
if (!(n ? tlb->V1 : tlb->V0)) {
return TLBRET_INVALID;
}
- if (rw == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {
+ if (rw == MEM_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {
return TLBRET_XI;
}
- if (rw == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {
+ if (rw == MEM_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {
return TLBRET_RI;
}
- if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
+ if (rw != MEM_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
*physical = tlb->PFN[n] | (address & (mask >> 1));
*prot = PAGE_READ;
if (n ? tlb->D1 : tlb->D0)
@@ -338,7 +338,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
CPUState *cs = CPU(mips_env_get_cpu(env));
int exception = 0, error_code = 0;
- if (rw == MMU_INST_FETCH) {
+ if (rw == MEM_INST_FETCH) {
error_code |= EXCP_INST_NOTAVAIL;
}
@@ -347,7 +347,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
case TLBRET_BADADDR:
/* Reference to kernel address from user mode or supervisor mode */
/* Reference to supervisor address from user mode */
- if (rw == MMU_DATA_STORE) {
+ if (rw == MEM_DATA_STORE) {
exception = EXCP_AdES;
} else {
exception = EXCP_AdEL;
@@ -355,7 +355,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
break;
case TLBRET_NOMATCH:
/* No TLB match for a mapped address */
- if (rw == MMU_DATA_STORE) {
+ if (rw == MEM_DATA_STORE) {
exception = EXCP_TLBS;
} else {
exception = EXCP_TLBL;
@@ -364,7 +364,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
break;
case TLBRET_INVALID:
/* TLB match with no valid bit */
- if (rw == MMU_DATA_STORE) {
+ if (rw == MEM_DATA_STORE) {
exception = EXCP_TLBS;
} else {
exception = EXCP_TLBL;
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index ea2f2ab..dd705f2 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2384,7 +2384,7 @@ void helper_wait(CPUMIPSState *env)
#if !defined(CONFIG_USER_ONLY)
void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
- MMUAccessType access_type,
+ MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
MIPSCPU *cpu = MIPS_CPU(cs);
@@ -2394,11 +2394,11 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
env->CP0_BadVAddr = addr;
- if (access_type == MMU_DATA_STORE) {
+ if (access_type == MEM_DATA_STORE) {
excp = EXCP_AdES;
} else {
excp = EXCP_AdEL;
- if (access_type == MMU_INST_FETCH) {
+ if (access_type == MEM_INST_FETCH) {
error_code |= EXCP_INST_NOTAVAIL;
}
}
@@ -2406,7 +2406,7 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
do_raise_exception_err(env, excp, error_code, retaddr);
}
-void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
+void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
int ret;
diff --git a/target-moxie/helper.c b/target-moxie/helper.c
index 330299f..a7b7b08 100644
--- a/target-moxie/helper.c
+++ b/target-moxie/helper.c
@@ -29,7 +29,7 @@
/* Try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
-void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
+void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
int ret;
diff --git a/target-openrisc/mmu_helper.c b/target-openrisc/mmu_helper.c
index a44d0aa..e26116c 100644
--- a/target-openrisc/mmu_helper.c
+++ b/target-openrisc/mmu_helper.c
@@ -25,7 +25,7 @@
#ifndef CONFIG_USER_ONLY
-void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
+void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
int ret;
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index 3eb3cd7..be436c1 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -2878,7 +2878,7 @@ void helper_check_tlb_flush(CPUPPCState *env)
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
-void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
+void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index 54a5177..136c6be 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -199,7 +199,7 @@ hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr)
vaddr &= 0x7fffffff;
}
- if (mmu_translate(env, vaddr, MMU_INST_FETCH, asc, &raddr, &prot, false)) {
+ if (mmu_translate(env, vaddr, MEM_INST_FETCH, asc, &raddr, &prot, false)) {
return -1;
}
return raddr;
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
index 99bc5e2..c56cfa0 100644
--- a/target-s390x/mem_helper.c
+++ b/target-s390x/mem_helper.c
@@ -36,7 +36,7 @@
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
-void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
+void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
int ret;
@@ -77,7 +77,7 @@ static void fast_memset(CPUS390XState *env, uint64_t dest, uint8_t byte,
int mmu_idx = cpu_mmu_index(env, false);
while (l > 0) {
- void *p = tlb_vaddr_to_host(env, dest, MMU_DATA_STORE, mmu_idx);
+ void *p = tlb_vaddr_to_host(env, dest, MEM_DATA_STORE, mmu_idx);
if (p) {
/* Access to the whole page in write mode granted. */
int l_adj = adj_len_to_page(l, dest);
@@ -100,8 +100,8 @@ static void fast_memmove(CPUS390XState *env, uint64_t dest, uint64_t src,
int mmu_idx = cpu_mmu_index(env, false);
while (l > 0) {
- void *src_p = tlb_vaddr_to_host(env, src, MMU_DATA_LOAD, mmu_idx);
- void *dest_p = tlb_vaddr_to_host(env, dest, MMU_DATA_STORE, mmu_idx);
+ void *src_p = tlb_vaddr_to_host(env, src, MEM_DATA_LOAD, mmu_idx);
+ void *dest_p = tlb_vaddr_to_host(env, dest, MEM_DATA_STORE, mmu_idx);
if (src_p && dest_p) {
/* Access to both whole pages granted. */
int l_adj = adj_len_to_page(l, src);
diff --git a/target-s390x/mmu_helper.c b/target-s390x/mmu_helper.c
index b11a027..5324dfb 100644
--- a/target-s390x/mmu_helper.c
+++ b/target-s390x/mmu_helper.c
@@ -71,7 +71,7 @@ static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr,
{
uint64_t tec;
- tec = vaddr | (rw == MMU_DATA_STORE ? FS_WRITE : FS_READ) | 4 | asc >> 46;
+ tec = vaddr | (rw == MEM_DATA_STORE ? FS_WRITE : FS_READ) | 4 | asc >> 46;
DPRINTF("%s: trans_exc_code=%016" PRIx64 "\n", __func__, tec);
@@ -88,7 +88,7 @@ static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr,
int ilen = ILEN_LATER;
uint64_t tec;
- tec = vaddr | (rw == MMU_DATA_STORE ? FS_WRITE : FS_READ) | asc >> 46;
+ tec = vaddr | (rw == MEM_DATA_STORE ? FS_WRITE : FS_READ) | asc >> 46;
DPRINTF("%s: trans_exc_code=%016" PRIx64 "\n", __func__, tec);
@@ -97,7 +97,7 @@ static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr,
}
/* Code accesses have an undefined ilc. */
- if (rw == MMU_INST_FETCH) {
+ if (rw == MEM_INST_FETCH) {
ilen = 2;
}
@@ -291,7 +291,7 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
r = mmu_translate_region(env, vaddr, asc, asce, level, raddr, flags, rw,
exc);
- if (rw == MMU_DATA_STORE && !(*flags & PAGE_WRITE)) {
+ if (rw == MEM_DATA_STORE && !(*flags & PAGE_WRITE)) {
trigger_prot_fault(env, vaddr, asc, rw, exc);
return -1;
}
@@ -348,7 +348,7 @@ int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
* Instruction: Primary
* Data: Secondary
*/
- if (rw == MMU_INST_FETCH) {
+ if (rw == MEM_INST_FETCH) {
r = mmu_translate_asce(env, vaddr, PSW_ASC_PRIMARY, env->cregs[1],
raddr, flags, rw, exc);
*flags &= ~(PAGE_READ | PAGE_WRITE);
diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index 0204b03..b00addd 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -24,7 +24,7 @@
#ifndef CONFIG_USER_ONLY
-void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
+void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
int ret;
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index a3d64a4..5134f1d 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -541,7 +541,7 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int sparc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
- MMUAccessType access_type,
+ MemoryAccessType access_type,
int mmu_idx,
uintptr_t retaddr);
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 6ce5ccc..042227c 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -2351,7 +2351,7 @@ void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
#if !defined(CONFIG_USER_ONLY)
void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
- MMUAccessType access_type,
+ MemoryAccessType access_type,
int mmu_idx,
uintptr_t retaddr)
{
@@ -2372,7 +2372,7 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
-void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
+void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
int ret;
diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c
index ac02e0a..ead24e7 100644
--- a/target-tricore/op_helper.c
+++ b/target-tricore/op_helper.c
@@ -2828,7 +2828,7 @@ static inline void QEMU_NORETURN do_raise_exception_err(CPUTriCoreState *env,
cpu_loop_exit(cs);
}
-void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
+void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
int ret;
diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
index 0872c29..1927efe 100644
--- a/target-unicore32/op_helper.c
+++ b/target-unicore32/op_helper.c
@@ -244,7 +244,7 @@ uint32_t HELPER(ror_cc)(CPUUniCore32State *env, uint32_t x, uint32_t i)
}
#ifndef CONFIG_USER_ONLY
-void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
+void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
int ret;
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index 7fe82a3..22c4471 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -414,7 +414,7 @@ hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int xtensa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
- MMUAccessType access_type,
+ MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr);
#define cpu_signal_handler cpu_xtensa_signal_handler
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index 0a4b214..11e0432 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -35,7 +35,7 @@
#include "qemu/timer.h"
void xtensa_cpu_do_unaligned_access(CPUState *cs,
- vaddr addr, MMUAccessType access_type,
+ vaddr addr, MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
XtensaCPU *cpu = XTENSA_CPU(cs);
@@ -49,7 +49,7 @@ void xtensa_cpu_do_unaligned_access(CPUState *cs,
}
}
-void tlb_fill(CPUState *cs, target_ulong vaddr, MMUAccessType access_type,
+void tlb_fill(CPUState *cs, target_ulong vaddr, MemoryAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
XtensaCPU *cpu = XTENSA_CPU(cs);
--
2.5.5
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [Qemu-devel] [PATCH v3 05/10] Rename MMUAccessType to MemoryAccessType
2016-07-20 5:02 ` [Qemu-devel] [PATCH v3 05/10] Rename MMUAccessType to MemoryAccessType Andrey Smirnov
@ 2016-07-20 9:34 ` David Gibson
0 siblings, 0 replies; 15+ messages in thread
From: David Gibson @ 2016-07-20 9:34 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: qemu-devel, Peter Maydell, qemu-ppc, qemu-arm, kvm
[-- Attachment #1: Type: text/plain, Size: 32057 bytes --]
On Tue, Jul 19, 2016 at 10:02:55PM -0700, Andrey Smirnov wrote:
> Rename MMUAccessType to MemoryAccessType and MMU_*
> constants to corresponding MEM_* constants, so it would be possible to
> re-use these defenitions in other, non MMU-related, contexts.
>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> include/exec/exec-all.h | 2 +-
> include/qom/cpu.h | 14 +++++++-------
> softmmu_template.h | 18 +++++++++---------
> target-alpha/cpu.h | 2 +-
> target-alpha/mem_helper.c | 4 ++--
> target-arm/internals.h | 2 +-
> target-arm/op_helper.c | 14 +++++++-------
> target-cris/op_helper.c | 2 +-
> target-i386/mem_helper.c | 2 +-
> target-lm32/op_helper.c | 2 +-
> target-m68k/op_helper.c | 2 +-
> target-microblaze/op_helper.c | 2 +-
> target-mips/cpu.h | 2 +-
> target-mips/helper.c | 14 +++++++-------
> target-mips/op_helper.c | 8 ++++----
> target-moxie/helper.c | 2 +-
> target-openrisc/mmu_helper.c | 2 +-
> target-ppc/mmu_helper.c | 2 +-
> target-s390x/helper.c | 2 +-
> target-s390x/mem_helper.c | 8 ++++----
> target-s390x/mmu_helper.c | 10 +++++-----
> target-sh4/op_helper.c | 2 +-
> target-sparc/cpu.h | 2 +-
> target-sparc/ldst_helper.c | 4 ++--
> target-tricore/op_helper.c | 2 +-
> target-unicore32/op_helper.c | 2 +-
> target-xtensa/cpu.h | 2 +-
> target-xtensa/op_helper.c | 4 ++--
> 28 files changed, 67 insertions(+), 67 deletions(-)
>
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index acda7b6..1d5c71e 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -361,7 +361,7 @@ extern uintptr_t tci_tb_ptr;
> struct MemoryRegion *iotlb_to_region(CPUState *cpu,
> hwaddr index, MemTxAttrs attrs);
>
> -void tlb_fill(CPUState *cpu, target_ulong addr, MMUAccessType access_type,
> +void tlb_fill(CPUState *cpu, target_ulong addr, MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr);
>
> #endif
> diff --git a/include/qom/cpu.h b/include/qom/cpu.h
> index a6c6ed8..b23b4b1 100644
> --- a/include/qom/cpu.h
> +++ b/include/qom/cpu.h
> @@ -60,11 +60,11 @@ typedef uint64_t vaddr;
> #define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU)
> #define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU)
>
> -typedef enum MMUAccessType {
> - MMU_DATA_LOAD = 0,
> - MMU_DATA_STORE = 1,
> - MMU_INST_FETCH = 2
> -} MMUAccessType;
> +typedef enum MemoryAccessType {
> + MEM_DATA_LOAD = 0,
> + MEM_DATA_STORE = 1,
> + MEM_INST_FETCH = 2
> +} MemoryAccessType;
>
> typedef struct CPUWatchpoint CPUWatchpoint;
>
> @@ -148,7 +148,7 @@ typedef struct CPUClass {
> void (*do_interrupt)(CPUState *cpu);
> CPUUnassignedAccess do_unassigned_access;
> void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
> - MMUAccessType access_type,
> + MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr);
> bool (*virtio_is_big_endian)(CPUState *cpu);
> int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
> @@ -723,7 +723,7 @@ static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr,
> }
>
> static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
> - MMUAccessType access_type,
> + MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr)
> {
> CPUClass *cc = CPU_GET_CLASS(cpu);
> diff --git a/softmmu_template.h b/softmmu_template.h
> index 284ab2c..e872a21 100644
> --- a/softmmu_template.h
> +++ b/softmmu_template.h
> @@ -67,10 +67,10 @@
> #endif
>
> #ifdef SOFTMMU_CODE_ACCESS
> -#define READ_ACCESS_TYPE MMU_INST_FETCH
> +#define READ_ACCESS_TYPE MEM_INST_FETCH
> #define ADDR_READ addr_code
> #else
> -#define READ_ACCESS_TYPE MMU_DATA_LOAD
> +#define READ_ACCESS_TYPE MEM_DATA_LOAD
> #define ADDR_READ addr_read
> #endif
>
> @@ -338,7 +338,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
> retaddr -= GETPC_ADJ;
>
> if (a_bits > 0 && (addr & ((1 << a_bits) - 1)) != 0) {
> - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
> + cpu_unaligned_access(ENV_GET_CPU(env), addr, MEM_DATA_STORE,
> mmu_idx, retaddr);
> }
>
> @@ -346,7 +346,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
> if ((addr & TARGET_PAGE_MASK)
> != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
> if (!VICTIM_TLB_HIT(addr_write, addr)) {
> - tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
> + tlb_fill(ENV_GET_CPU(env), addr, MEM_DATA_STORE, mmu_idx, retaddr);
> }
> tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
> }
> @@ -381,7 +381,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
> tlb_addr2 = env->tlb_table[mmu_idx][index2].addr_write;
> if (page2 != (tlb_addr2 & (TARGET_PAGE_MASK | TLB_INVALID_MASK))
> && !VICTIM_TLB_HIT(addr_write, page2)) {
> - tlb_fill(ENV_GET_CPU(env), page2, MMU_DATA_STORE,
> + tlb_fill(ENV_GET_CPU(env), page2, MEM_DATA_STORE,
> mmu_idx, retaddr);
> }
>
> @@ -421,7 +421,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
> retaddr -= GETPC_ADJ;
>
> if (a_bits > 0 && (addr & ((1 << a_bits) - 1)) != 0) {
> - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
> + cpu_unaligned_access(ENV_GET_CPU(env), addr, MEM_DATA_STORE,
> mmu_idx, retaddr);
> }
>
> @@ -429,7 +429,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
> if ((addr & TARGET_PAGE_MASK)
> != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
> if (!VICTIM_TLB_HIT(addr_write, addr)) {
> - tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
> + tlb_fill(ENV_GET_CPU(env), addr, MEM_DATA_STORE, mmu_idx, retaddr);
> }
> tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
> }
> @@ -464,7 +464,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
> tlb_addr2 = env->tlb_table[mmu_idx][index2].addr_write;
> if (page2 != (tlb_addr2 & (TARGET_PAGE_MASK | TLB_INVALID_MASK))
> && !VICTIM_TLB_HIT(addr_write, page2)) {
> - tlb_fill(ENV_GET_CPU(env), page2, MMU_DATA_STORE,
> + tlb_fill(ENV_GET_CPU(env), page2, MEM_DATA_STORE,
> mmu_idx, retaddr);
> }
>
> @@ -504,7 +504,7 @@ void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
> != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
> /* TLB entry is for a different page */
> if (!VICTIM_TLB_HIT(addr_write, addr)) {
> - tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
> + tlb_fill(ENV_GET_CPU(env), addr, MEM_DATA_STORE, mmu_idx, retaddr);
> }
> }
> }
> diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
> index ac5e801..700f616 100644
> --- a/target-alpha/cpu.h
> +++ b/target-alpha/cpu.h
> @@ -323,7 +323,7 @@ hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
> int alpha_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
> int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
> void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
> - MMUAccessType access_type,
> + MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr);
>
> #define cpu_list alpha_cpu_list
> diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
> index 1b2be50..d6ffabe 100644
> --- a/target-alpha/mem_helper.c
> +++ b/target-alpha/mem_helper.c
> @@ -99,7 +99,7 @@ uint64_t helper_stq_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
> }
>
> void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> - MMUAccessType access_type,
> + MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr)
> {
> AlphaCPU *cpu = ALPHA_CPU(cs);
> @@ -145,7 +145,7 @@ void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr,
> NULL, it means that the function was called in C code (i.e. not
> from generated code or from helper.c) */
> /* XXX: fix it to restore all registers */
> -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
> +void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr)
> {
> int ret;
> diff --git a/target-arm/internals.h b/target-arm/internals.h
> index cd57401..d6fafc5 100644
> --- a/target-arm/internals.h
> +++ b/target-arm/internals.h
> @@ -477,7 +477,7 @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
>
> /* Raise a data fault alignment exception for the specified virtual address */
> void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
> - MMUAccessType access_type,
> + MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr);
>
> /* Call the EL change hook if one has been registered */
> diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
> index 3e8588e..74526a2 100644
> --- a/target-arm/op_helper.c
> +++ b/target-arm/op_helper.c
> @@ -117,7 +117,7 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
> * NULL, it means that the function was called in C code (i.e. not
> * from generated code or from helper.c)
> */
> -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
> +void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr)
> {
> bool ret;
> @@ -149,14 +149,14 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
> /* For insn and data aborts we assume there is no instruction syndrome
> * information; this is always true for exceptions reported to EL1.
> */
> - if (access_type == MMU_INST_FETCH) {
> + if (access_type == MEM_INST_FETCH) {
> syn = syn_insn_abort(same_el, 0, fi.s1ptw, syn);
> exc = EXCP_PREFETCH_ABORT;
> } else {
> syn = merge_syn_data_abort(env->exception.syndrome, target_el,
> same_el, fi.s1ptw,
> - access_type == MMU_DATA_STORE, syn);
> - if (access_type == MMU_DATA_STORE
> + access_type == MEM_DATA_STORE, syn);
> + if (access_type == MEM_DATA_STORE
> && arm_feature(env, ARM_FEATURE_V6)) {
> fsr |= (1 << 11);
> }
> @@ -171,7 +171,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
>
> /* Raise a data fault alignment exception for the specified virtual address */
> void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
> - MMUAccessType access_type,
> + MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr)
> {
> ARMCPU *cpu = ARM_CPU(cs);
> @@ -199,12 +199,12 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
> env->exception.fsr = 0x1;
> }
>
> - if (access_type == MMU_DATA_STORE && arm_feature(env, ARM_FEATURE_V6)) {
> + if (access_type == MEM_DATA_STORE && arm_feature(env, ARM_FEATURE_V6)) {
> env->exception.fsr |= (1 << 11);
> }
>
> syn = merge_syn_data_abort(env->exception.syndrome, target_el,
> - same_el, 0, access_type == MMU_DATA_STORE,
> + same_el, 0, access_type == MEM_DATA_STORE,
> 0x21);
> raise_exception(env, EXCP_DATA_ABORT, syn, target_el);
> }
> diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
> index 5043039..c83e955 100644
> --- a/target-cris/op_helper.c
> +++ b/target-cris/op_helper.c
> @@ -41,7 +41,7 @@
> /* Try to fill the TLB and return an exception if error. If retaddr is
> NULL, it means that the function was called in C code (i.e. not
> from generated code or from helper.c) */
> -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
> +void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr)
> {
> CRISCPU *cpu = CRIS_CPU(cs);
> diff --git a/target-i386/mem_helper.c b/target-i386/mem_helper.c
> index 5bc0594..679322c 100644
> --- a/target-i386/mem_helper.c
> +++ b/target-i386/mem_helper.c
> @@ -140,7 +140,7 @@ void helper_boundl(CPUX86State *env, target_ulong a0, int v)
> * from generated code or from helper.c)
> */
> /* XXX: fix it to restore all registers */
> -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
> +void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr)
> {
> int ret;
> diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c
> index 2177c8a..bc78f3c 100644
> --- a/target-lm32/op_helper.c
> +++ b/target-lm32/op_helper.c
> @@ -144,7 +144,7 @@ uint32_t HELPER(rcsr_jrx)(CPULM32State *env)
> * NULL, it means that the function was called in C code (i.e. not
> * from generated code or from helper.c)
> */
> -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
> +void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr)
> {
> int ret;
> diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
> index e41ae46..43f556e 100644
> --- a/target-m68k/op_helper.c
> +++ b/target-m68k/op_helper.c
> @@ -39,7 +39,7 @@ static inline void do_interrupt_m68k_hardirq(CPUM68KState *env)
> /* Try to fill the TLB and return an exception if error. If retaddr is
> NULL, it means that the function was called in C code (i.e. not
> from generated code or from helper.c) */
> -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
> +void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr)
> {
> int ret;
> diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
> index 4a856e6..1e1690a 100644
> --- a/target-microblaze/op_helper.c
> +++ b/target-microblaze/op_helper.c
> @@ -33,7 +33,7 @@
> * NULL, it means that the function was called in C code (i.e. not
> * from generated code or from helper.c)
> */
> -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
> +void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr)
> {
> int ret;
> diff --git a/target-mips/cpu.h b/target-mips/cpu.h
> index 5182dc7..55a3e34 100644
> --- a/target-mips/cpu.h
> +++ b/target-mips/cpu.h
> @@ -657,7 +657,7 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
> int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
> int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
> void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
> - MMUAccessType access_type,
> + MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr);
>
> #if !defined(CONFIG_USER_ONLY)
> diff --git a/target-mips/helper.c b/target-mips/helper.c
> index 9fbca26..bd3f7cd 100644
> --- a/target-mips/helper.c
> +++ b/target-mips/helper.c
> @@ -88,13 +88,13 @@ int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
> if (!(n ? tlb->V1 : tlb->V0)) {
> return TLBRET_INVALID;
> }
> - if (rw == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {
> + if (rw == MEM_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {
> return TLBRET_XI;
> }
> - if (rw == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {
> + if (rw == MEM_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {
> return TLBRET_RI;
> }
> - if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
> + if (rw != MEM_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
> *physical = tlb->PFN[n] | (address & (mask >> 1));
> *prot = PAGE_READ;
> if (n ? tlb->D1 : tlb->D0)
> @@ -338,7 +338,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
> CPUState *cs = CPU(mips_env_get_cpu(env));
> int exception = 0, error_code = 0;
>
> - if (rw == MMU_INST_FETCH) {
> + if (rw == MEM_INST_FETCH) {
> error_code |= EXCP_INST_NOTAVAIL;
> }
>
> @@ -347,7 +347,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
> case TLBRET_BADADDR:
> /* Reference to kernel address from user mode or supervisor mode */
> /* Reference to supervisor address from user mode */
> - if (rw == MMU_DATA_STORE) {
> + if (rw == MEM_DATA_STORE) {
> exception = EXCP_AdES;
> } else {
> exception = EXCP_AdEL;
> @@ -355,7 +355,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
> break;
> case TLBRET_NOMATCH:
> /* No TLB match for a mapped address */
> - if (rw == MMU_DATA_STORE) {
> + if (rw == MEM_DATA_STORE) {
> exception = EXCP_TLBS;
> } else {
> exception = EXCP_TLBL;
> @@ -364,7 +364,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
> break;
> case TLBRET_INVALID:
> /* TLB match with no valid bit */
> - if (rw == MMU_DATA_STORE) {
> + if (rw == MEM_DATA_STORE) {
> exception = EXCP_TLBS;
> } else {
> exception = EXCP_TLBL;
> diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
> index ea2f2ab..dd705f2 100644
> --- a/target-mips/op_helper.c
> +++ b/target-mips/op_helper.c
> @@ -2384,7 +2384,7 @@ void helper_wait(CPUMIPSState *env)
> #if !defined(CONFIG_USER_ONLY)
>
> void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> - MMUAccessType access_type,
> + MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr)
> {
> MIPSCPU *cpu = MIPS_CPU(cs);
> @@ -2394,11 +2394,11 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
>
> env->CP0_BadVAddr = addr;
>
> - if (access_type == MMU_DATA_STORE) {
> + if (access_type == MEM_DATA_STORE) {
> excp = EXCP_AdES;
> } else {
> excp = EXCP_AdEL;
> - if (access_type == MMU_INST_FETCH) {
> + if (access_type == MEM_INST_FETCH) {
> error_code |= EXCP_INST_NOTAVAIL;
> }
> }
> @@ -2406,7 +2406,7 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> do_raise_exception_err(env, excp, error_code, retaddr);
> }
>
> -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
> +void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr)
> {
> int ret;
> diff --git a/target-moxie/helper.c b/target-moxie/helper.c
> index 330299f..a7b7b08 100644
> --- a/target-moxie/helper.c
> +++ b/target-moxie/helper.c
> @@ -29,7 +29,7 @@
> /* Try to fill the TLB and return an exception if error. If retaddr is
> NULL, it means that the function was called in C code (i.e. not
> from generated code or from helper.c) */
> -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
> +void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr)
> {
> int ret;
> diff --git a/target-openrisc/mmu_helper.c b/target-openrisc/mmu_helper.c
> index a44d0aa..e26116c 100644
> --- a/target-openrisc/mmu_helper.c
> +++ b/target-openrisc/mmu_helper.c
> @@ -25,7 +25,7 @@
>
> #ifndef CONFIG_USER_ONLY
>
> -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
> +void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr)
> {
> int ret;
> diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
> index 3eb3cd7..be436c1 100644
> --- a/target-ppc/mmu_helper.c
> +++ b/target-ppc/mmu_helper.c
> @@ -2878,7 +2878,7 @@ void helper_check_tlb_flush(CPUPPCState *env)
> NULL, it means that the function was called in C code (i.e. not
> from generated code or from helper.c) */
> /* XXX: fix it to restore all registers */
> -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
> +void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr)
> {
> PowerPCCPU *cpu = POWERPC_CPU(cs);
> diff --git a/target-s390x/helper.c b/target-s390x/helper.c
> index 54a5177..136c6be 100644
> --- a/target-s390x/helper.c
> +++ b/target-s390x/helper.c
> @@ -199,7 +199,7 @@ hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr)
> vaddr &= 0x7fffffff;
> }
>
> - if (mmu_translate(env, vaddr, MMU_INST_FETCH, asc, &raddr, &prot, false)) {
> + if (mmu_translate(env, vaddr, MEM_INST_FETCH, asc, &raddr, &prot, false)) {
> return -1;
> }
> return raddr;
> diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
> index 99bc5e2..c56cfa0 100644
> --- a/target-s390x/mem_helper.c
> +++ b/target-s390x/mem_helper.c
> @@ -36,7 +36,7 @@
> NULL, it means that the function was called in C code (i.e. not
> from generated code or from helper.c) */
> /* XXX: fix it to restore all registers */
> -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
> +void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr)
> {
> int ret;
> @@ -77,7 +77,7 @@ static void fast_memset(CPUS390XState *env, uint64_t dest, uint8_t byte,
> int mmu_idx = cpu_mmu_index(env, false);
>
> while (l > 0) {
> - void *p = tlb_vaddr_to_host(env, dest, MMU_DATA_STORE, mmu_idx);
> + void *p = tlb_vaddr_to_host(env, dest, MEM_DATA_STORE, mmu_idx);
> if (p) {
> /* Access to the whole page in write mode granted. */
> int l_adj = adj_len_to_page(l, dest);
> @@ -100,8 +100,8 @@ static void fast_memmove(CPUS390XState *env, uint64_t dest, uint64_t src,
> int mmu_idx = cpu_mmu_index(env, false);
>
> while (l > 0) {
> - void *src_p = tlb_vaddr_to_host(env, src, MMU_DATA_LOAD, mmu_idx);
> - void *dest_p = tlb_vaddr_to_host(env, dest, MMU_DATA_STORE, mmu_idx);
> + void *src_p = tlb_vaddr_to_host(env, src, MEM_DATA_LOAD, mmu_idx);
> + void *dest_p = tlb_vaddr_to_host(env, dest, MEM_DATA_STORE, mmu_idx);
> if (src_p && dest_p) {
> /* Access to both whole pages granted. */
> int l_adj = adj_len_to_page(l, src);
> diff --git a/target-s390x/mmu_helper.c b/target-s390x/mmu_helper.c
> index b11a027..5324dfb 100644
> --- a/target-s390x/mmu_helper.c
> +++ b/target-s390x/mmu_helper.c
> @@ -71,7 +71,7 @@ static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr,
> {
> uint64_t tec;
>
> - tec = vaddr | (rw == MMU_DATA_STORE ? FS_WRITE : FS_READ) | 4 | asc >> 46;
> + tec = vaddr | (rw == MEM_DATA_STORE ? FS_WRITE : FS_READ) | 4 | asc >> 46;
>
> DPRINTF("%s: trans_exc_code=%016" PRIx64 "\n", __func__, tec);
>
> @@ -88,7 +88,7 @@ static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr,
> int ilen = ILEN_LATER;
> uint64_t tec;
>
> - tec = vaddr | (rw == MMU_DATA_STORE ? FS_WRITE : FS_READ) | asc >> 46;
> + tec = vaddr | (rw == MEM_DATA_STORE ? FS_WRITE : FS_READ) | asc >> 46;
>
> DPRINTF("%s: trans_exc_code=%016" PRIx64 "\n", __func__, tec);
>
> @@ -97,7 +97,7 @@ static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr,
> }
>
> /* Code accesses have an undefined ilc. */
> - if (rw == MMU_INST_FETCH) {
> + if (rw == MEM_INST_FETCH) {
> ilen = 2;
> }
>
> @@ -291,7 +291,7 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
>
> r = mmu_translate_region(env, vaddr, asc, asce, level, raddr, flags, rw,
> exc);
> - if (rw == MMU_DATA_STORE && !(*flags & PAGE_WRITE)) {
> + if (rw == MEM_DATA_STORE && !(*flags & PAGE_WRITE)) {
> trigger_prot_fault(env, vaddr, asc, rw, exc);
> return -1;
> }
> @@ -348,7 +348,7 @@ int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
> * Instruction: Primary
> * Data: Secondary
> */
> - if (rw == MMU_INST_FETCH) {
> + if (rw == MEM_INST_FETCH) {
> r = mmu_translate_asce(env, vaddr, PSW_ASC_PRIMARY, env->cregs[1],
> raddr, flags, rw, exc);
> *flags &= ~(PAGE_READ | PAGE_WRITE);
> diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
> index 0204b03..b00addd 100644
> --- a/target-sh4/op_helper.c
> +++ b/target-sh4/op_helper.c
> @@ -24,7 +24,7 @@
>
> #ifndef CONFIG_USER_ONLY
>
> -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
> +void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr)
> {
> int ret;
> diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
> index a3d64a4..5134f1d 100644
> --- a/target-sparc/cpu.h
> +++ b/target-sparc/cpu.h
> @@ -541,7 +541,7 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
> int sparc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
> int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
> void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
> - MMUAccessType access_type,
> + MemoryAccessType access_type,
> int mmu_idx,
> uintptr_t retaddr);
>
> diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
> index 6ce5ccc..042227c 100644
> --- a/target-sparc/ldst_helper.c
> +++ b/target-sparc/ldst_helper.c
> @@ -2351,7 +2351,7 @@ void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
>
> #if !defined(CONFIG_USER_ONLY)
> void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> - MMUAccessType access_type,
> + MemoryAccessType access_type,
> int mmu_idx,
> uintptr_t retaddr)
> {
> @@ -2372,7 +2372,7 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> NULL, it means that the function was called in C code (i.e. not
> from generated code or from helper.c) */
> /* XXX: fix it to restore all registers */
> -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
> +void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr)
> {
> int ret;
> diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c
> index ac02e0a..ead24e7 100644
> --- a/target-tricore/op_helper.c
> +++ b/target-tricore/op_helper.c
> @@ -2828,7 +2828,7 @@ static inline void QEMU_NORETURN do_raise_exception_err(CPUTriCoreState *env,
> cpu_loop_exit(cs);
> }
>
> -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
> +void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr)
> {
> int ret;
> diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
> index 0872c29..1927efe 100644
> --- a/target-unicore32/op_helper.c
> +++ b/target-unicore32/op_helper.c
> @@ -244,7 +244,7 @@ uint32_t HELPER(ror_cc)(CPUUniCore32State *env, uint32_t x, uint32_t i)
> }
>
> #ifndef CONFIG_USER_ONLY
> -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
> +void tlb_fill(CPUState *cs, target_ulong addr, MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr)
> {
> int ret;
> diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
> index 7fe82a3..22c4471 100644
> --- a/target-xtensa/cpu.h
> +++ b/target-xtensa/cpu.h
> @@ -414,7 +414,7 @@ hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
> int xtensa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
> int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
> void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
> - MMUAccessType access_type,
> + MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr);
>
> #define cpu_signal_handler cpu_xtensa_signal_handler
> diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
> index 0a4b214..11e0432 100644
> --- a/target-xtensa/op_helper.c
> +++ b/target-xtensa/op_helper.c
> @@ -35,7 +35,7 @@
> #include "qemu/timer.h"
>
> void xtensa_cpu_do_unaligned_access(CPUState *cs,
> - vaddr addr, MMUAccessType access_type,
> + vaddr addr, MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr)
> {
> XtensaCPU *cpu = XTENSA_CPU(cs);
> @@ -49,7 +49,7 @@ void xtensa_cpu_do_unaligned_access(CPUState *cs,
> }
> }
>
> -void tlb_fill(CPUState *cs, target_ulong vaddr, MMUAccessType access_type,
> +void tlb_fill(CPUState *cs, target_ulong vaddr, MemoryAccessType access_type,
> int mmu_idx, uintptr_t retaddr)
> {
> XtensaCPU *cpu = XTENSA_CPU(cs);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH v3 06/10] Change signature of cpu_memory_rw_debug() to avoid casting
2016-07-20 5:02 [Qemu-devel] [PATCH v3 00/10] Support non-direct memory writes in cpu_memory_rw_debug Andrey Smirnov
` (4 preceding siblings ...)
2016-07-20 5:02 ` [Qemu-devel] [PATCH v3 05/10] Rename MMUAccessType to MemoryAccessType Andrey Smirnov
@ 2016-07-20 5:02 ` Andrey Smirnov
2016-07-20 5:02 ` [Qemu-devel] [PATCH v3 07/10] Convert cpu_memory_rw_debug to use MemoryAccessType Andrey Smirnov
` (3 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Andrey Smirnov @ 2016-07-20 5:02 UTC (permalink / raw)
To: qemu-devel
Cc: Andrey Smirnov, Peter Maydell, David Gibson, qemu-ppc, qemu-arm,
kvm
Change signature of cpu_memory_rw_debug() to expectet void * as a buffer
instead of uint8_t * to avoid forcing the caller of the function to do a
type cast.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
exec.c | 6 ++++--
hw/i386/kvmvapic.c | 10 +++++-----
include/exec/cpu-all.h | 2 +-
include/exec/softmmu-semi.h | 8 ++++----
target-arm/arm-semi.c | 2 +-
target-arm/kvm64.c | 8 ++++----
target-i386/helper.c | 4 ++--
target-i386/kvm.c | 8 ++++----
target-ppc/kvm.c | 8 ++++----
target-s390x/kvm.c | 6 +++---
target-xtensa/xtensa-semi.c | 6 +++---
11 files changed, 35 insertions(+), 33 deletions(-)
diff --git a/exec.c b/exec.c
index e2425c5..f20b216 100644
--- a/exec.c
+++ b/exec.c
@@ -2436,11 +2436,12 @@ MemoryRegion *get_system_io(void)
/* physical memory access (slow version, mainly for debug) */
#if defined(CONFIG_USER_ONLY)
int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
- uint8_t *buf, int len, int is_write)
+ void *b, int len, int is_write)
{
int l, flags;
target_ulong page;
void * p;
+ uint8_t *buf = b;
while (len > 0) {
page = addr & TARGET_PAGE_MASK;
@@ -3617,11 +3618,12 @@ void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val)
/* virtual memory access for debug (includes writing to ROM) */
int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
- uint8_t *buf, int len, int is_write)
+ void *b, int len, int is_write)
{
int l;
hwaddr phys_addr;
target_ulong page;
+ uint8_t *buf = b;
while (len > 0) {
int asidx;
diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c
index 3bf1ddd..c684675 100644
--- a/hw/i386/kvmvapic.c
+++ b/hw/i386/kvmvapic.c
@@ -261,7 +261,7 @@ instruction_ok:
* and update the cached values.
*/
if (cpu_memory_rw_debug(cs, ip + instr->addr_offset,
- (void *)&real_tpr_addr,
+ &real_tpr_addr,
sizeof(real_tpr_addr), 0) < 0) {
return -1;
}
@@ -349,7 +349,7 @@ static int get_kpcr_number(X86CPU *cpu)
} QEMU_PACKED kpcr;
if (cpu_memory_rw_debug(CPU(cpu), env->segs[R_FS].base,
- (void *)&kpcr, sizeof(kpcr), 0) < 0 ||
+ &kpcr, sizeof(kpcr), 0) < 0 ||
kpcr.self != env->segs[R_FS].base) {
return -1;
}
@@ -388,7 +388,7 @@ static void patch_call(VAPICROMState *s, X86CPU *cpu, target_ulong ip,
offset = cpu_to_le32(target - ip - 5);
patch_byte(cpu, ip, 0xe8); /* call near */
- cpu_memory_rw_debug(CPU(cpu), ip + 1, (void *)&offset, sizeof(offset), 1);
+ cpu_memory_rw_debug(CPU(cpu), ip + 1, &offset, sizeof(offset), 1);
}
static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)
@@ -434,8 +434,8 @@ static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)
break;
case 0xc7: /* mov imm32, r/m32 (c7/0) */
patch_byte(cpu, ip, 0x68); /* push imm32 */
- cpu_memory_rw_debug(cs, ip + 6, (void *)&imm32, sizeof(imm32), 0);
- cpu_memory_rw_debug(cs, ip + 1, (void *)&imm32, sizeof(imm32), 1);
+ cpu_memory_rw_debug(cs, ip + 6, &imm32, sizeof(imm32), 0);
+ cpu_memory_rw_debug(cs, ip + 1, &imm32, sizeof(imm32), 1);
patch_call(s, cpu, ip + 5, handlers->set_tpr);
break;
case 0xff: /* push r/m32 */
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index b6a7059..ad498d0 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -310,7 +310,7 @@ void dump_opcount_info(FILE *f, fprintf_function cpu_fprintf);
#endif /* !CONFIG_USER_ONLY */
int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
- uint8_t *buf, int len, int is_write);
+ void *buf, int len, int is_write);
int cpu_exec(CPUState *cpu);
diff --git a/include/exec/softmmu-semi.h b/include/exec/softmmu-semi.h
index 7eefad8..263aa25 100644
--- a/include/exec/softmmu-semi.h
+++ b/include/exec/softmmu-semi.h
@@ -14,7 +14,7 @@ static inline uint64_t softmmu_tget64(CPUArchState *env, target_ulong addr)
{
uint64_t val;
- cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 8, 0);
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 8, 0);
return tswap64(val);
}
@@ -22,7 +22,7 @@ static inline uint32_t softmmu_tget32(CPUArchState *env, target_ulong addr)
{
uint32_t val;
- cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 4, 0);
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 4, 0);
return tswap32(val);
}
@@ -43,14 +43,14 @@ static inline void softmmu_tput64(CPUArchState *env,
target_ulong addr, uint64_t val)
{
val = tswap64(val);
- cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 8, 1);
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 8, 1);
}
static inline void softmmu_tput32(CPUArchState *env,
target_ulong addr, uint32_t val)
{
val = tswap32(val);
- cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 4, 1);
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 4, 1);
}
#define put_user_u64(arg, p) ({ softmmu_tput64(env, p, arg) ; 0; })
#define put_user_u32(arg, p) ({ softmmu_tput32(env, p, arg) ; 0; })
diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c
index 7cac873..bd4bf13 100644
--- a/target-arm/arm-semi.c
+++ b/target-arm/arm-semi.c
@@ -187,7 +187,7 @@ static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err)
/* The size is always stored in big-endian order, extract
the value. We assume the size always fit in 32 bits. */
uint32_t size;
- cpu_memory_rw_debug(cs, arm_flen_buf(cpu) + 32, (uint8_t *)&size, 4, 0);
+ cpu_memory_rw_debug(cs, arm_flen_buf(cpu) + 32, &size, 4, 0);
size = be32_to_cpu(size);
if (is_a64(env)) {
env->xregs[0] = size;
diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c
index 5faa76c..7ba5acd 100644
--- a/target-arm/kvm64.c
+++ b/target-arm/kvm64.c
@@ -874,8 +874,8 @@ static const uint32_t brk_insn = 0xd4200000;
int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
{
if (have_guest_debug) {
- if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) ||
- cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk_insn, 4, 1)) {
+ if (cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn, 4, 0) ||
+ cpu_memory_rw_debug(cs, bp->pc, &brk_insn, 4, 1)) {
return -EINVAL;
}
return 0;
@@ -890,9 +890,9 @@ int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
static uint32_t brk;
if (have_guest_debug) {
- if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk, 4, 0) ||
+ if (cpu_memory_rw_debug(cs, bp->pc, &brk, 4, 0) ||
brk != brk_insn ||
- cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) {
+ cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn, 4, 1)) {
return -EINVAL;
}
return 0;
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 1c250b8..3e8d86f 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -1286,8 +1286,8 @@ int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
index = selector & ~7;
ptr = dt->base + index;
if ((index + 7) > dt->limit
- || cpu_memory_rw_debug(cs, ptr, (uint8_t *)&e1, sizeof(e1), 0) != 0
- || cpu_memory_rw_debug(cs, ptr+4, (uint8_t *)&e2, sizeof(e2), 0) != 0)
+ || cpu_memory_rw_debug(cs, ptr, &e1, sizeof(e1), 0) != 0
+ || cpu_memory_rw_debug(cs, ptr + 4, &e2, sizeof(e2), 0) != 0)
return 0;
*base = ((e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000));
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index 9327523..46e6a64 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -2911,10 +2911,10 @@ static int kvm_handle_tpr_access(X86CPU *cpu)
int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
{
- static const uint8_t int3 = 0xcc;
+ uint8_t int3 = 0xcc;
- if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
- cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
+ if (cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn, 1, 0) ||
+ cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 1)) {
return -EINVAL;
}
return 0;
@@ -2925,7 +2925,7 @@ int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
uint8_t int3;
if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
- cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
+ cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn, 1, 1)) {
return -EINVAL;
}
return 0;
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 7a8f555..73ac879 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -1454,9 +1454,9 @@ int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
/* Mixed endian case is not handled */
uint32_t sc = debug_inst_opcode;
- if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
+ if (cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn,
sizeof(sc), 0) ||
- cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 1)) {
+ cpu_memory_rw_debug(cs, bp->pc, &sc, sizeof(sc), 1)) {
return -EINVAL;
}
@@ -1467,9 +1467,9 @@ int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
{
uint32_t sc;
- if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 0) ||
+ if (cpu_memory_rw_debug(cs, bp->pc, &sc, sizeof(sc), 0) ||
sc != debug_inst_opcode ||
- cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
+ cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn,
sizeof(sc), 1)) {
return -EINVAL;
}
diff --git a/target-s390x/kvm.c b/target-s390x/kvm.c
index 2991bff..565b1b2 100644
--- a/target-s390x/kvm.c
+++ b/target-s390x/kvm.c
@@ -671,9 +671,9 @@ static const uint8_t diag_501[] = {0x83, 0x24, 0x05, 0x01};
int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
{
- if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
+ if (cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn,
sizeof(diag_501), 0) ||
- cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)diag_501,
+ cpu_memory_rw_debug(cs, bp->pc, diag_501,
sizeof(diag_501), 1)) {
return -EINVAL;
}
@@ -688,7 +688,7 @@ int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
return -EINVAL;
} else if (memcmp(t, diag_501, sizeof(diag_501))) {
return -EINVAL;
- } else if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
+ } else if (cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn,
sizeof(diag_501), 1)) {
return -EINVAL;
}
diff --git a/target-xtensa/xtensa-semi.c b/target-xtensa/xtensa-semi.c
index 370e365..ec199ac 100644
--- a/target-xtensa/xtensa-semi.c
+++ b/target-xtensa/xtensa-semi.c
@@ -202,7 +202,7 @@ void HELPER(simcall)(CPUXtensaState *env)
for (i = 0; i < ARRAY_SIZE(name); ++i) {
rc = cpu_memory_rw_debug(cs, regs[3] + i,
- (uint8_t *)name + i, 1, 0);
+ &name[i], 1, 0);
if (rc != 0 || name[i] == 0) {
break;
}
@@ -247,7 +247,7 @@ void HELPER(simcall)(CPUXtensaState *env)
if (target_tv) {
cpu_memory_rw_debug(cs, target_tv,
- (uint8_t *)target_tvv, sizeof(target_tvv), 0);
+ target_tvv, sizeof(target_tvv), 0);
tv.tv_sec = (int32_t)tswap32(target_tvv[0]);
tv.tv_usec = (int32_t)tswap32(target_tvv[1]);
}
@@ -282,7 +282,7 @@ void HELPER(simcall)(CPUXtensaState *env)
argv.argptr[0] = tswap32(regs[3] + offsetof(struct Argv, text));
cpu_memory_rw_debug(cs,
- regs[3], (uint8_t *)&argv, sizeof(argv), 1);
+ regs[3], &argv, sizeof(argv), 1);
}
break;
--
2.5.5
^ permalink raw reply related [flat|nested] 15+ messages in thread* [Qemu-devel] [PATCH v3 07/10] Convert cpu_memory_rw_debug to use MemoryAccessType
2016-07-20 5:02 [Qemu-devel] [PATCH v3 00/10] Support non-direct memory writes in cpu_memory_rw_debug Andrey Smirnov
` (5 preceding siblings ...)
2016-07-20 5:02 ` [Qemu-devel] [PATCH v3 06/10] Change signature of cpu_memory_rw_debug() to avoid casting Andrey Smirnov
@ 2016-07-20 5:02 ` Andrey Smirnov
2016-07-20 9:45 ` David Gibson
2016-07-20 5:02 ` [Qemu-devel] [PATCH v3 08/10] Convert address_space_rw " Andrey Smirnov
` (2 subsequent siblings)
9 siblings, 1 reply; 15+ messages in thread
From: Andrey Smirnov @ 2016-07-20 5:02 UTC (permalink / raw)
To: qemu-devel
Cc: Andrey Smirnov, Peter Maydell, David Gibson, qemu-ppc, qemu-arm,
kvm
Convert cpu_memory_rw_debug() to use MemoryAccessType as a way of
specifying memory reads/writes. This makes caller code be more obvious
in what it does (previously one had to interpret 0 or 1 and remember the
semantics of the last boolean argument of the function).
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
cpus.c | 2 +-
disas.c | 4 ++--
exec.c | 14 ++++++++++----
gdbstub.c | 3 ++-
hw/i386/kvmvapic.c | 20 +++++++++++---------
include/exec/cpu-all.h | 2 +-
include/exec/softmmu-semi.h | 16 ++++++++--------
monitor.c | 3 ++-
target-arm/arm-semi.c | 2 +-
target-arm/kvm64.c | 12 ++++++++----
target-i386/helper.c | 7 ++++---
target-i386/kvm.c | 9 +++++----
target-ppc/kvm.c | 9 +++++----
target-s390x/kvm.c | 9 +++++----
target-sparc/mmu_helper.c | 8 ++++++--
target-xtensa/xtensa-semi.c | 10 +++++-----
16 files changed, 76 insertions(+), 54 deletions(-)
diff --git a/cpus.c b/cpus.c
index 84c3520..ce19a13 100644
--- a/cpus.c
+++ b/cpus.c
@@ -1691,7 +1691,7 @@ void qmp_memsave(int64_t addr, int64_t size, const char *filename,
l = sizeof(buf);
if (l > size)
l = size;
- if (cpu_memory_rw_debug(cpu, addr, buf, l, 0) != 0) {
+ if (cpu_memory_rw_debug(cpu, addr, buf, l, MEM_DATA_LOAD) != 0) {
error_setg(errp, "Invalid addr 0x%016" PRIx64 "/size %" PRId64
" specified", orig_addr, orig_size);
goto exit;
diff --git a/disas.c b/disas.c
index 05a7a12..c72c0dc 100644
--- a/disas.c
+++ b/disas.c
@@ -39,7 +39,7 @@ target_read_memory (bfd_vma memaddr,
{
CPUDebug *s = container_of(info, CPUDebug, info);
- cpu_memory_rw_debug(s->cpu, memaddr, myaddr, length, 0);
+ cpu_memory_rw_debug(s->cpu, memaddr, myaddr, length, MEM_DATA_LOAD);
return 0;
}
@@ -358,7 +358,7 @@ monitor_read_memory (bfd_vma memaddr, bfd_byte *myaddr, int length,
if (monitor_disas_is_physical) {
cpu_physical_memory_read(memaddr, myaddr, length);
} else {
- cpu_memory_rw_debug(s->cpu, memaddr, myaddr, length, 0);
+ cpu_memory_rw_debug(s->cpu, memaddr, myaddr, length, MEM_DATA_LOAD);
}
return 0;
}
diff --git a/exec.c b/exec.c
index f20b216..995ff60 100644
--- a/exec.c
+++ b/exec.c
@@ -2436,13 +2436,16 @@ MemoryRegion *get_system_io(void)
/* physical memory access (slow version, mainly for debug) */
#if defined(CONFIG_USER_ONLY)
int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
- void *b, int len, int is_write)
+ void *b, int len, MemoryAccessType access_type)
{
int l, flags;
target_ulong page;
void * p;
uint8_t *buf = b;
+ g_assert(access_type == MEM_DATA_STORE ||
+ access_type == MEM_DATA_LOAD);
+
while (len > 0) {
page = addr & TARGET_PAGE_MASK;
l = (page + TARGET_PAGE_SIZE) - addr;
@@ -2451,7 +2454,7 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
flags = page_get_flags(page);
if (!(flags & PAGE_VALID))
return -1;
- if (is_write) {
+ if (access_type == MEM_DATA_STORE) {
if (!(flags & PAGE_WRITE))
return -1;
/* XXX: this code should not depend on lock_user */
@@ -3618,13 +3621,16 @@ void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val)
/* virtual memory access for debug (includes writing to ROM) */
int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
- void *b, int len, int is_write)
+ void *b, int len, MemoryAccessType access_type)
{
int l;
hwaddr phys_addr;
target_ulong page;
uint8_t *buf = b;
+ g_assert(access_type == MEM_DATA_STORE ||
+ access_type == MEM_DATA_LOAD);
+
while (len > 0) {
int asidx;
MemTxAttrs attrs;
@@ -3639,7 +3645,7 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
if (l > len)
l = len;
phys_addr += (addr & ~TARGET_PAGE_MASK);
- if (is_write) {
+ if (access_type == MEM_DATA_STORE) {
cpu_physical_memory_write_rom(cpu->cpu_ases[asidx].as,
phys_addr, buf, l);
} else {
diff --git a/gdbstub.c b/gdbstub.c
index 5da66f1..9c4cbe4 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -51,7 +51,8 @@ static inline int target_memory_rw_debug(CPUState *cpu, target_ulong addr,
if (cc->memory_rw_debug) {
return cc->memory_rw_debug(cpu, addr, buf, len, is_write);
}
- return cpu_memory_rw_debug(cpu, addr, buf, len, is_write);
+ return cpu_memory_rw_debug(cpu, addr, buf, len,
+ is_write ? MEM_DATA_STORE : MEM_DATA_LOAD);
}
enum {
diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c
index c684675..8e15c0b 100644
--- a/hw/i386/kvmvapic.c
+++ b/hw/i386/kvmvapic.c
@@ -233,7 +233,7 @@ static int evaluate_tpr_instruction(VAPICROMState *s, X86CPU *cpu,
continue;
}
if (cpu_memory_rw_debug(cs, ip - instr->length, opcode,
- sizeof(opcode), 0) < 0) {
+ sizeof(opcode), MEM_DATA_LOAD) < 0) {
return -1;
}
if (opcode_matches(opcode, instr)) {
@@ -243,7 +243,8 @@ static int evaluate_tpr_instruction(VAPICROMState *s, X86CPU *cpu,
}
return -1;
} else {
- if (cpu_memory_rw_debug(cs, ip, opcode, sizeof(opcode), 0) < 0) {
+ if (cpu_memory_rw_debug(cs, ip, opcode,
+ sizeof(opcode), MEM_DATA_LOAD) < 0) {
return -1;
}
for (i = 0; i < ARRAY_SIZE(tpr_instr); i++) {
@@ -262,7 +263,7 @@ instruction_ok:
*/
if (cpu_memory_rw_debug(cs, ip + instr->addr_offset,
&real_tpr_addr,
- sizeof(real_tpr_addr), 0) < 0) {
+ sizeof(real_tpr_addr), MEM_DATA_LOAD) < 0) {
return -1;
}
real_tpr_addr = le32_to_cpu(real_tpr_addr);
@@ -349,7 +350,7 @@ static int get_kpcr_number(X86CPU *cpu)
} QEMU_PACKED kpcr;
if (cpu_memory_rw_debug(CPU(cpu), env->segs[R_FS].base,
- &kpcr, sizeof(kpcr), 0) < 0 ||
+ &kpcr, sizeof(kpcr), MEM_DATA_LOAD) < 0 ||
kpcr.self != env->segs[R_FS].base) {
return -1;
}
@@ -378,7 +379,7 @@ static int vapic_enable(VAPICROMState *s, X86CPU *cpu)
static void patch_byte(X86CPU *cpu, target_ulong addr, uint8_t byte)
{
- cpu_memory_rw_debug(CPU(cpu), addr, &byte, 1, 1);
+ cpu_memory_rw_debug(CPU(cpu), addr, &byte, 1, MEM_DATA_STORE);
}
static void patch_call(VAPICROMState *s, X86CPU *cpu, target_ulong ip,
@@ -388,7 +389,8 @@ static void patch_call(VAPICROMState *s, X86CPU *cpu, target_ulong ip,
offset = cpu_to_le32(target - ip - 5);
patch_byte(cpu, ip, 0xe8); /* call near */
- cpu_memory_rw_debug(CPU(cpu), ip + 1, &offset, sizeof(offset), 1);
+ cpu_memory_rw_debug(CPU(cpu), ip + 1, &offset,
+ sizeof(offset), MEM_DATA_STORE);
}
static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)
@@ -415,7 +417,7 @@ static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)
pause_all_vcpus();
- cpu_memory_rw_debug(cs, ip, opcode, sizeof(opcode), 0);
+ cpu_memory_rw_debug(cs, ip, opcode, sizeof(opcode), MEM_DATA_LOAD);
switch (opcode[0]) {
case 0x89: /* mov r32 to r/m32 */
@@ -434,8 +436,8 @@ static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)
break;
case 0xc7: /* mov imm32, r/m32 (c7/0) */
patch_byte(cpu, ip, 0x68); /* push imm32 */
- cpu_memory_rw_debug(cs, ip + 6, &imm32, sizeof(imm32), 0);
- cpu_memory_rw_debug(cs, ip + 1, &imm32, sizeof(imm32), 1);
+ cpu_memory_rw_debug(cs, ip + 6, &imm32, sizeof(imm32), MEM_DATA_LOAD);
+ cpu_memory_rw_debug(cs, ip + 1, &imm32, sizeof(imm32), MEM_DATA_STORE);
patch_call(s, cpu, ip + 5, handlers->set_tpr);
break;
case 0xff: /* push r/m32 */
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index ad498d0..8cde65d 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -310,7 +310,7 @@ void dump_opcount_info(FILE *f, fprintf_function cpu_fprintf);
#endif /* !CONFIG_USER_ONLY */
int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
- void *buf, int len, int is_write);
+ void *buf, int len, MemoryAccessType access_type);
int cpu_exec(CPUState *cpu);
diff --git a/include/exec/softmmu-semi.h b/include/exec/softmmu-semi.h
index 263aa25..4dde38c 100644
--- a/include/exec/softmmu-semi.h
+++ b/include/exec/softmmu-semi.h
@@ -14,7 +14,7 @@ static inline uint64_t softmmu_tget64(CPUArchState *env, target_ulong addr)
{
uint64_t val;
- cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 8, 0);
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 8, MEM_DATA_LOAD);
return tswap64(val);
}
@@ -22,7 +22,7 @@ static inline uint32_t softmmu_tget32(CPUArchState *env, target_ulong addr)
{
uint32_t val;
- cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 4, 0);
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 4, MEM_DATA_LOAD);
return tswap32(val);
}
@@ -30,7 +30,7 @@ static inline uint32_t softmmu_tget8(CPUArchState *env, target_ulong addr)
{
uint8_t val;
- cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 1, 0);
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 1, MEM_DATA_LOAD);
return val;
}
@@ -43,14 +43,14 @@ static inline void softmmu_tput64(CPUArchState *env,
target_ulong addr, uint64_t val)
{
val = tswap64(val);
- cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 8, 1);
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 8, MEM_DATA_STORE);
}
static inline void softmmu_tput32(CPUArchState *env,
target_ulong addr, uint32_t val)
{
val = tswap32(val);
- cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 4, 1);
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 4, MEM_DATA_STORE);
}
#define put_user_u64(arg, p) ({ softmmu_tput64(env, p, arg) ; 0; })
#define put_user_u32(arg, p) ({ softmmu_tput32(env, p, arg) ; 0; })
@@ -63,7 +63,7 @@ static void *softmmu_lock_user(CPUArchState *env,
/* TODO: Make this something that isn't fixed size. */
p = malloc(len);
if (p && copy) {
- cpu_memory_rw_debug(ENV_GET_CPU(env), addr, p, len, 0);
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, p, len, MEM_DATA_LOAD);
}
return p;
}
@@ -79,7 +79,7 @@ static char *softmmu_lock_user_string(CPUArchState *env, target_ulong addr)
return NULL;
}
do {
- cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &c, 1, 0);
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &c, 1, MEM_DATA_LOAD);
addr++;
*(p++) = c;
} while (c);
@@ -90,7 +90,7 @@ static void softmmu_unlock_user(CPUArchState *env, void *p, target_ulong addr,
target_ulong len)
{
if (len) {
- cpu_memory_rw_debug(ENV_GET_CPU(env), addr, p, len, 1);
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, p, len, MEM_DATA_STORE);
}
free(p);
}
diff --git a/monitor.c b/monitor.c
index d0ff246..226b060 100644
--- a/monitor.c
+++ b/monitor.c
@@ -1269,7 +1269,8 @@ static void memory_dump(Monitor *mon, int count, int format, int wsize,
if (is_physical) {
cpu_physical_memory_read(addr, buf, l);
} else {
- if (cpu_memory_rw_debug(mon_get_cpu(), addr, buf, l, 0) < 0) {
+ if (cpu_memory_rw_debug(mon_get_cpu(), addr, buf,
+ l, MEM_DATA_LOAD) < 0) {
monitor_printf(mon, " Cannot access memory\n");
break;
}
diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c
index bd4bf13..157fb0b 100644
--- a/target-arm/arm-semi.c
+++ b/target-arm/arm-semi.c
@@ -187,7 +187,7 @@ static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err)
/* The size is always stored in big-endian order, extract
the value. We assume the size always fit in 32 bits. */
uint32_t size;
- cpu_memory_rw_debug(cs, arm_flen_buf(cpu) + 32, &size, 4, 0);
+ cpu_memory_rw_debug(cs, arm_flen_buf(cpu) + 32, &size, 4, MEM_DATA_LOAD);
size = be32_to_cpu(size);
if (is_a64(env)) {
env->xregs[0] = size;
diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c
index 7ba5acd..9bd821e 100644
--- a/target-arm/kvm64.c
+++ b/target-arm/kvm64.c
@@ -874,8 +874,10 @@ static const uint32_t brk_insn = 0xd4200000;
int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
{
if (have_guest_debug) {
- if (cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn, 4, 0) ||
- cpu_memory_rw_debug(cs, bp->pc, &brk_insn, 4, 1)) {
+ if (cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn,
+ 4, MEM_DATA_LOAD) ||
+ cpu_memory_rw_debug(cs, bp->pc, &brk_insn,
+ 4, MEM_DATA_STORE)) {
return -EINVAL;
}
return 0;
@@ -890,9 +892,11 @@ int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
static uint32_t brk;
if (have_guest_debug) {
- if (cpu_memory_rw_debug(cs, bp->pc, &brk, 4, 0) ||
+ if (cpu_memory_rw_debug(cs, bp->pc, &brk,
+ 4, MEM_DATA_LOAD) ||
brk != brk_insn ||
- cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn, 4, 1)) {
+ cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn,
+ 4, MEM_DATA_STORE)) {
return -EINVAL;
}
return 0;
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 3e8d86f..8161807 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -555,7 +555,8 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
cpu_fprintf(f, "Code=");
for (i = 0; i < DUMP_CODE_BYTES_TOTAL; i++) {
- if (cpu_memory_rw_debug(cs, base - offs + i, &code, 1, 0) == 0) {
+ if (cpu_memory_rw_debug(cs, base - offs + i, &code,
+ 1, MEM_DATA_LOAD) == 0) {
snprintf(codestr, sizeof(codestr), "%02x", code);
} else {
snprintf(codestr, sizeof(codestr), "??");
@@ -1286,8 +1287,8 @@ int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
index = selector & ~7;
ptr = dt->base + index;
if ((index + 7) > dt->limit
- || cpu_memory_rw_debug(cs, ptr, &e1, sizeof(e1), 0) != 0
- || cpu_memory_rw_debug(cs, ptr + 4, &e2, sizeof(e2), 0) != 0)
+ || cpu_memory_rw_debug(cs, ptr, &e1, sizeof(e1), MEM_DATA_LOAD) != 0
+ || cpu_memory_rw_debug(cs, ptr + 4, &e2, sizeof(e2), MEM_DATA_LOAD) != 0)
return 0;
*base = ((e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000));
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index 46e6a64..8d01142 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -2913,8 +2913,8 @@ int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
{
uint8_t int3 = 0xcc;
- if (cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn, 1, 0) ||
- cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 1)) {
+ if (cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn, 1, MEM_DATA_LOAD) ||
+ cpu_memory_rw_debug(cs, bp->pc, &int3, 1, MEM_DATA_STORE)) {
return -EINVAL;
}
return 0;
@@ -2924,8 +2924,9 @@ int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
{
uint8_t int3;
- if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
- cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn, 1, 1)) {
+ if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, MEM_DATA_LOAD) ||
+ int3 != 0xcc ||
+ cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn, 1, MEM_DATA_STORE)) {
return -EINVAL;
}
return 0;
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 73ac879..8ffe6e0 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -1455,8 +1455,8 @@ int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
uint32_t sc = debug_inst_opcode;
if (cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn,
- sizeof(sc), 0) ||
- cpu_memory_rw_debug(cs, bp->pc, &sc, sizeof(sc), 1)) {
+ sizeof(sc), MEM_DATA_LOAD) ||
+ cpu_memory_rw_debug(cs, bp->pc, &sc, sizeof(sc), MEM_DATA_STORE)) {
return -EINVAL;
}
@@ -1467,10 +1467,11 @@ int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
{
uint32_t sc;
- if (cpu_memory_rw_debug(cs, bp->pc, &sc, sizeof(sc), 0) ||
+ if (cpu_memory_rw_debug(cs, bp->pc, &sc,
+ sizeof(sc), MEM_DATA_LOAD) ||
sc != debug_inst_opcode ||
cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn,
- sizeof(sc), 1)) {
+ sizeof(sc), MEM_DATA_STORE)) {
return -EINVAL;
}
diff --git a/target-s390x/kvm.c b/target-s390x/kvm.c
index 565b1b2..c279ddb 100644
--- a/target-s390x/kvm.c
+++ b/target-s390x/kvm.c
@@ -672,9 +672,9 @@ int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
{
if (cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn,
- sizeof(diag_501), 0) ||
+ sizeof(diag_501), MEM_DATA_LOAD) ||
cpu_memory_rw_debug(cs, bp->pc, diag_501,
- sizeof(diag_501), 1)) {
+ sizeof(diag_501), MEM_DATA_STORE)) {
return -EINVAL;
}
return 0;
@@ -684,12 +684,13 @@ int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
{
uint8_t t[sizeof(diag_501)];
- if (cpu_memory_rw_debug(cs, bp->pc, t, sizeof(diag_501), 0)) {
+ if (cpu_memory_rw_debug(cs, bp->pc, t,
+ sizeof(diag_501), MEM_DATA_LOAD)) {
return -EINVAL;
} else if (memcmp(t, diag_501, sizeof(diag_501))) {
return -EINVAL;
} else if (cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn,
- sizeof(diag_501), 1)) {
+ sizeof(diag_501), MEM_DATA_STORE)) {
return -EINVAL;
}
diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
index 32b629f..5040603 100644
--- a/target-sparc/mmu_helper.c
+++ b/target-sparc/mmu_helper.c
@@ -398,7 +398,10 @@ int sparc_cpu_memory_rw_debug(CPUState *cs, vaddr address,
/* Handle access before this window. */
if (addr < fp) {
len1 = fp - addr;
- if (cpu_memory_rw_debug(cs, addr, buf, len1, is_write) != 0) {
+ if (cpu_memory_rw_debug(cs, addr, buf, len1,
+ is_write ?
+ MEM_DATA_STORE :
+ MEM_DATA_LOAD) != 0) {
return -1;
}
addr += len1;
@@ -434,7 +437,8 @@ int sparc_cpu_memory_rw_debug(CPUState *cs, vaddr address,
}
}
}
- return cpu_memory_rw_debug(cs, addr, buf, len, is_write);
+ return cpu_memory_rw_debug(cs, addr, buf, len,
+ is_write ? MEM_DATA_STORE : MEM_DATA_LOAD);
}
#else /* !TARGET_SPARC64 */
diff --git a/target-xtensa/xtensa-semi.c b/target-xtensa/xtensa-semi.c
index ec199ac..c775375 100644
--- a/target-xtensa/xtensa-semi.c
+++ b/target-xtensa/xtensa-semi.c
@@ -202,7 +202,7 @@ void HELPER(simcall)(CPUXtensaState *env)
for (i = 0; i < ARRAY_SIZE(name); ++i) {
rc = cpu_memory_rw_debug(cs, regs[3] + i,
- &name[i], 1, 0);
+ &name[i], 1, MEM_DATA_LOAD);
if (rc != 0 || name[i] == 0) {
break;
}
@@ -246,8 +246,8 @@ void HELPER(simcall)(CPUXtensaState *env)
FD_SET(fd, &fdset);
if (target_tv) {
- cpu_memory_rw_debug(cs, target_tv,
- target_tvv, sizeof(target_tvv), 0);
+ cpu_memory_rw_debug(cs, target_tv, target_tvv,
+ sizeof(target_tvv), MEM_DATA_LOAD);
tv.tv_sec = (int32_t)tswap32(target_tvv[0]);
tv.tv_usec = (int32_t)tswap32(target_tvv[1]);
}
@@ -281,8 +281,8 @@ void HELPER(simcall)(CPUXtensaState *env)
};
argv.argptr[0] = tswap32(regs[3] + offsetof(struct Argv, text));
- cpu_memory_rw_debug(cs,
- regs[3], &argv, sizeof(argv), 1);
+ cpu_memory_rw_debug(cs, regs[3], &argv,
+ sizeof(argv), MEM_DATA_STORE);
}
break;
--
2.5.5
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [Qemu-devel] [PATCH v3 07/10] Convert cpu_memory_rw_debug to use MemoryAccessType
2016-07-20 5:02 ` [Qemu-devel] [PATCH v3 07/10] Convert cpu_memory_rw_debug to use MemoryAccessType Andrey Smirnov
@ 2016-07-20 9:45 ` David Gibson
0 siblings, 0 replies; 15+ messages in thread
From: David Gibson @ 2016-07-20 9:45 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: qemu-devel, Peter Maydell, qemu-ppc, qemu-arm, kvm
[-- Attachment #1: Type: text/plain, Size: 663 bytes --]
On Tue, Jul 19, 2016 at 10:02:57PM -0700, Andrey Smirnov wrote:
> Convert cpu_memory_rw_debug() to use MemoryAccessType as a way of
> specifying memory reads/writes. This makes caller code be more obvious
> in what it does (previously one had to interpret 0 or 1 and remember the
> semantics of the last boolean argument of the function).
>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH v3 08/10] Convert address_space_rw to use MemoryAccessType
2016-07-20 5:02 [Qemu-devel] [PATCH v3 00/10] Support non-direct memory writes in cpu_memory_rw_debug Andrey Smirnov
` (6 preceding siblings ...)
2016-07-20 5:02 ` [Qemu-devel] [PATCH v3 07/10] Convert cpu_memory_rw_debug to use MemoryAccessType Andrey Smirnov
@ 2016-07-20 5:02 ` Andrey Smirnov
2016-07-21 1:47 ` David Gibson
2016-07-20 5:02 ` [Qemu-devel] [PATCH v3 09/10] gdbstub: Convert target_memory_rw_debug " Andrey Smirnov
2016-07-20 5:03 ` [Qemu-devel] [PATCH v3 10/10] exec: Use address_space_rw to handle reads and wirtes Andrey Smirnov
9 siblings, 1 reply; 15+ messages in thread
From: Andrey Smirnov @ 2016-07-20 5:02 UTC (permalink / raw)
To: qemu-devel
Cc: Andrey Smirnov, Peter Maydell, David Gibson, qemu-ppc, qemu-arm,
kvm
Convert address_space_rw() to use MemoryAccessType following the
conversion of cpu_memory_rw_debug().
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
exec.c | 14 +++++++++-----
include/exec/memory.h | 7 +++++--
kvm-all.c | 8 +++++---
scripts/coverity-model.c | 9 +++++++--
4 files changed, 26 insertions(+), 12 deletions(-)
diff --git a/exec.c b/exec.c
index 995ff60..5557cc9 100644
--- a/exec.c
+++ b/exec.c
@@ -2726,12 +2726,16 @@ MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr,
}
MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
- uint8_t *buf, int len, bool is_write)
+ uint8_t *buf, int len,
+ MemoryAccessType access_type)
{
- if (is_write) {
+ switch (access_type) {
+ case MEM_DATA_STORE:
return address_space_write(as, addr, attrs, buf, len);
- } else {
+ case MEM_DATA_LOAD:
return address_space_read(as, addr, attrs, buf, len);
+ default:
+ abort();
}
}
@@ -2739,7 +2743,7 @@ void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
int len, int is_write)
{
address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED,
- buf, len, is_write);
+ buf, len, is_write ? MEM_DATA_STORE : MEM_DATA_LOAD);
}
enum write_rom_type {
@@ -3651,7 +3655,7 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
} else {
address_space_rw(cpu->cpu_ases[asidx].as, phys_addr,
MEMTXATTRS_UNSPECIFIED,
- buf, l, 0);
+ buf, l, access_type);
}
len -= l;
buf += l;
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 7851ca9..da56c0e 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -22,6 +22,7 @@
#define DIRTY_MEMORY_NUM 3 /* num of dirty bits */
#include "exec/cpu-common.h"
+#include "qom/cpu.h"
#ifndef CONFIG_USER_ONLY
#include "exec/hwaddr.h"
#endif
@@ -1284,11 +1285,13 @@ void address_space_destroy(AddressSpace *as);
* @addr: address within that address space
* @attrs: memory transaction attributes
* @buf: buffer with the data transferred
- * @is_write: indicates the transfer direction
+ * @access_type: indicates the transfer direction (only valid values
+ * are MEM_DATA_LOAD for data reads and MEM_DATA_STORE for data
+ * writes)
*/
MemTxResult address_space_rw(AddressSpace *as, hwaddr addr,
MemTxAttrs attrs, uint8_t *buf,
- int len, bool is_write);
+ int len, MemoryAccessType access_type);
/**
* address_space_write: write to address space.
diff --git a/kvm-all.c b/kvm-all.c
index a88f917..ed45a95 100644
--- a/kvm-all.c
+++ b/kvm-all.c
@@ -1767,11 +1767,12 @@ static void kvm_handle_io(uint16_t port, MemTxAttrs attrs, void *data, int direc
{
int i;
uint8_t *ptr = data;
+ MemoryAccessType access_type =
+ (direction == KVM_EXIT_IO_OUT) ? MEM_DATA_STORE : MEM_DATA_LOAD;
for (i = 0; i < count; i++) {
address_space_rw(&address_space_io, port, attrs,
- ptr, size,
- direction == KVM_EXIT_IO_OUT);
+ ptr, size, access_type);
ptr += size;
}
}
@@ -1947,7 +1948,8 @@ int kvm_cpu_exec(CPUState *cpu)
run->mmio.phys_addr, attrs,
run->mmio.data,
run->mmio.len,
- run->mmio.is_write);
+ run->mmio.is_write ?
+ MEM_DATA_STORE : MEM_DATA_LOAD);
ret = 0;
break;
case KVM_EXIT_IRQ_WINDOW_OPEN:
diff --git a/scripts/coverity-model.c b/scripts/coverity-model.c
index ee5bf9d..c5603b5 100644
--- a/scripts/coverity-model.c
+++ b/scripts/coverity-model.c
@@ -68,13 +68,18 @@ static void __bufread(uint8_t *buf, ssize_t len)
}
MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
- uint8_t *buf, int len, bool is_write)
+ uint8_t *buf, int len,
+ MemoryAccessType access_type)
{
MemTxResult result;
// TODO: investigate impact of treating reads as producing
// tainted data, with __coverity_tainted_data_argument__(buf).
- if (is_write) __bufread(buf, len); else __bufwrite(buf, len);
+ if (access_type == MEM_DATA_STORE) {
+ __bufread(buf, len);
+ } else {
+ __bufwrite(buf, len);
+ }
return result;
}
--
2.5.5
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [Qemu-devel] [PATCH v3 08/10] Convert address_space_rw to use MemoryAccessType
2016-07-20 5:02 ` [Qemu-devel] [PATCH v3 08/10] Convert address_space_rw " Andrey Smirnov
@ 2016-07-21 1:47 ` David Gibson
0 siblings, 0 replies; 15+ messages in thread
From: David Gibson @ 2016-07-21 1:47 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: qemu-devel, Peter Maydell, qemu-ppc, qemu-arm, kvm
[-- Attachment #1: Type: text/plain, Size: 5544 bytes --]
On Tue, Jul 19, 2016 at 10:02:58PM -0700, Andrey Smirnov wrote:
> Convert address_space_rw() to use MemoryAccessType following the
> conversion of cpu_memory_rw_debug().
>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> exec.c | 14 +++++++++-----
> include/exec/memory.h | 7 +++++--
> kvm-all.c | 8 +++++---
> scripts/coverity-model.c | 9 +++++++--
> 4 files changed, 26 insertions(+), 12 deletions(-)
>
> diff --git a/exec.c b/exec.c
> index 995ff60..5557cc9 100644
> --- a/exec.c
> +++ b/exec.c
> @@ -2726,12 +2726,16 @@ MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr,
> }
>
> MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
> - uint8_t *buf, int len, bool is_write)
> + uint8_t *buf, int len,
> + MemoryAccessType access_type)
> {
> - if (is_write) {
> + switch (access_type) {
> + case MEM_DATA_STORE:
> return address_space_write(as, addr, attrs, buf, len);
> - } else {
> + case MEM_DATA_LOAD:
> return address_space_read(as, addr, attrs, buf, len);
> + default:
> + abort();
> }
> }
>
> @@ -2739,7 +2743,7 @@ void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
> int len, int is_write)
> {
> address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED,
> - buf, len, is_write);
> + buf, len, is_write ? MEM_DATA_STORE : MEM_DATA_LOAD);
> }
>
> enum write_rom_type {
> @@ -3651,7 +3655,7 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
> } else {
> address_space_rw(cpu->cpu_ases[asidx].as, phys_addr,
> MEMTXATTRS_UNSPECIFIED,
> - buf, l, 0);
> + buf, l, access_type);
> }
> len -= l;
> buf += l;
> diff --git a/include/exec/memory.h b/include/exec/memory.h
> index 7851ca9..da56c0e 100644
> --- a/include/exec/memory.h
> +++ b/include/exec/memory.h
> @@ -22,6 +22,7 @@
> #define DIRTY_MEMORY_NUM 3 /* num of dirty bits */
>
> #include "exec/cpu-common.h"
> +#include "qom/cpu.h"
> #ifndef CONFIG_USER_ONLY
> #include "exec/hwaddr.h"
> #endif
> @@ -1284,11 +1285,13 @@ void address_space_destroy(AddressSpace *as);
> * @addr: address within that address space
> * @attrs: memory transaction attributes
> * @buf: buffer with the data transferred
> - * @is_write: indicates the transfer direction
> + * @access_type: indicates the transfer direction (only valid values
> + * are MEM_DATA_LOAD for data reads and MEM_DATA_STORE for data
> + * writes)
> */
> MemTxResult address_space_rw(AddressSpace *as, hwaddr addr,
> MemTxAttrs attrs, uint8_t *buf,
> - int len, bool is_write);
> + int len, MemoryAccessType access_type);
>
> /**
> * address_space_write: write to address space.
> diff --git a/kvm-all.c b/kvm-all.c
> index a88f917..ed45a95 100644
> --- a/kvm-all.c
> +++ b/kvm-all.c
> @@ -1767,11 +1767,12 @@ static void kvm_handle_io(uint16_t port, MemTxAttrs attrs, void *data, int direc
> {
> int i;
> uint8_t *ptr = data;
> + MemoryAccessType access_type =
> + (direction == KVM_EXIT_IO_OUT) ? MEM_DATA_STORE : MEM_DATA_LOAD;
>
> for (i = 0; i < count; i++) {
> address_space_rw(&address_space_io, port, attrs,
> - ptr, size,
> - direction == KVM_EXIT_IO_OUT);
> + ptr, size, access_type);
> ptr += size;
> }
> }
> @@ -1947,7 +1948,8 @@ int kvm_cpu_exec(CPUState *cpu)
> run->mmio.phys_addr, attrs,
> run->mmio.data,
> run->mmio.len,
> - run->mmio.is_write);
> + run->mmio.is_write ?
> + MEM_DATA_STORE : MEM_DATA_LOAD);
> ret = 0;
> break;
> case KVM_EXIT_IRQ_WINDOW_OPEN:
> diff --git a/scripts/coverity-model.c b/scripts/coverity-model.c
> index ee5bf9d..c5603b5 100644
> --- a/scripts/coverity-model.c
> +++ b/scripts/coverity-model.c
> @@ -68,13 +68,18 @@ static void __bufread(uint8_t *buf, ssize_t len)
> }
>
> MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
> - uint8_t *buf, int len, bool is_write)
> + uint8_t *buf, int len,
> + MemoryAccessType access_type)
> {
> MemTxResult result;
>
> // TODO: investigate impact of treating reads as producing
> // tainted data, with __coverity_tainted_data_argument__(buf).
> - if (is_write) __bufread(buf, len); else __bufwrite(buf, len);
> + if (access_type == MEM_DATA_STORE) {
> + __bufread(buf, len);
> + } else {
> + __bufwrite(buf, len);
> + }
>
> return result;
> }
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH v3 09/10] gdbstub: Convert target_memory_rw_debug to use MemoryAccessType
2016-07-20 5:02 [Qemu-devel] [PATCH v3 00/10] Support non-direct memory writes in cpu_memory_rw_debug Andrey Smirnov
` (7 preceding siblings ...)
2016-07-20 5:02 ` [Qemu-devel] [PATCH v3 08/10] Convert address_space_rw " Andrey Smirnov
@ 2016-07-20 5:02 ` Andrey Smirnov
2016-07-21 1:48 ` David Gibson
2016-07-20 5:03 ` [Qemu-devel] [PATCH v3 10/10] exec: Use address_space_rw to handle reads and wirtes Andrey Smirnov
9 siblings, 1 reply; 15+ messages in thread
From: Andrey Smirnov @ 2016-07-20 5:02 UTC (permalink / raw)
To: qemu-devel
Cc: Andrey Smirnov, Peter Maydell, David Gibson, qemu-ppc, qemu-arm,
kvm
Convert target_memory_rw_debug to use MemoryAccessType as to follow
similar conversion of cpu_memory_rw_debug.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
gdbstub.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index 9c4cbe4..c215672 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -44,15 +44,17 @@
#endif
static inline int target_memory_rw_debug(CPUState *cpu, target_ulong addr,
- uint8_t *buf, int len, bool is_write)
+ uint8_t *buf, int len,
+ MemoryAccessType access_type)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
if (cc->memory_rw_debug) {
+ const bool is_write = (access_type == MEM_DATA_STORE);
return cc->memory_rw_debug(cpu, addr, buf, len, is_write);
}
- return cpu_memory_rw_debug(cpu, addr, buf, len,
- is_write ? MEM_DATA_STORE : MEM_DATA_LOAD);
+
+ return cpu_memory_rw_debug(cpu, addr, buf, len, access_type);
}
enum {
@@ -966,7 +968,8 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
break;
}
- if (target_memory_rw_debug(s->g_cpu, addr, mem_buf, len, false) != 0) {
+ if (target_memory_rw_debug(s->g_cpu, addr, mem_buf,
+ len, MEM_DATA_LOAD) != 0) {
put_packet (s, "E14");
} else {
memtohex(buf, mem_buf, len);
@@ -988,7 +991,7 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
}
hextomem(mem_buf, p, len);
if (target_memory_rw_debug(s->g_cpu, addr, mem_buf, len,
- true) != 0) {
+ MEM_DATA_STORE) != 0) {
put_packet(s, "E14");
} else {
put_packet(s, "OK");
--
2.5.5
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [Qemu-devel] [PATCH v3 09/10] gdbstub: Convert target_memory_rw_debug to use MemoryAccessType
2016-07-20 5:02 ` [Qemu-devel] [PATCH v3 09/10] gdbstub: Convert target_memory_rw_debug " Andrey Smirnov
@ 2016-07-21 1:48 ` David Gibson
0 siblings, 0 replies; 15+ messages in thread
From: David Gibson @ 2016-07-21 1:48 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: qemu-devel, Peter Maydell, qemu-ppc, qemu-arm, kvm
[-- Attachment #1: Type: text/plain, Size: 2391 bytes --]
On Tue, Jul 19, 2016 at 10:02:59PM -0700, Andrey Smirnov wrote:
> Convert target_memory_rw_debug to use MemoryAccessType as to follow
> similar conversion of cpu_memory_rw_debug.
>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> gdbstub.c | 13 ++++++++-----
> 1 file changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/gdbstub.c b/gdbstub.c
> index 9c4cbe4..c215672 100644
> --- a/gdbstub.c
> +++ b/gdbstub.c
> @@ -44,15 +44,17 @@
> #endif
>
> static inline int target_memory_rw_debug(CPUState *cpu, target_ulong addr,
> - uint8_t *buf, int len, bool is_write)
> + uint8_t *buf, int len,
> + MemoryAccessType access_type)
> {
> CPUClass *cc = CPU_GET_CLASS(cpu);
>
> if (cc->memory_rw_debug) {
> + const bool is_write = (access_type == MEM_DATA_STORE);
> return cc->memory_rw_debug(cpu, addr, buf, len, is_write);
> }
> - return cpu_memory_rw_debug(cpu, addr, buf, len,
> - is_write ? MEM_DATA_STORE : MEM_DATA_LOAD);
> +
> + return cpu_memory_rw_debug(cpu, addr, buf, len, access_type);
> }
>
> enum {
> @@ -966,7 +968,8 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
> break;
> }
>
> - if (target_memory_rw_debug(s->g_cpu, addr, mem_buf, len, false) != 0) {
> + if (target_memory_rw_debug(s->g_cpu, addr, mem_buf,
> + len, MEM_DATA_LOAD) != 0) {
> put_packet (s, "E14");
> } else {
> memtohex(buf, mem_buf, len);
> @@ -988,7 +991,7 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
> }
> hextomem(mem_buf, p, len);
> if (target_memory_rw_debug(s->g_cpu, addr, mem_buf, len,
> - true) != 0) {
> + MEM_DATA_STORE) != 0) {
> put_packet(s, "E14");
> } else {
> put_packet(s, "OK");
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH v3 10/10] exec: Use address_space_rw to handle reads and wirtes
2016-07-20 5:02 [Qemu-devel] [PATCH v3 00/10] Support non-direct memory writes in cpu_memory_rw_debug Andrey Smirnov
` (8 preceding siblings ...)
2016-07-20 5:02 ` [Qemu-devel] [PATCH v3 09/10] gdbstub: Convert target_memory_rw_debug " Andrey Smirnov
@ 2016-07-20 5:03 ` Andrey Smirnov
9 siblings, 0 replies; 15+ messages in thread
From: Andrey Smirnov @ 2016-07-20 5:03 UTC (permalink / raw)
To: qemu-devel
Cc: Andrey Smirnov, Peter Maydell, David Gibson, qemu-ppc, qemu-arm,
kvm
Use address_space_rw to handle reads and wirtes in cpu_memory_rw_debug()
this way it becomes possible to modify memory mapped registers through
GDB connection.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
exec.c | 55 ++++++++++++++++++++++++++++++++++++++++---------------
gdbstub.c | 2 +-
include/qom/cpu.h | 3 ++-
3 files changed, 43 insertions(+), 17 deletions(-)
diff --git a/exec.c b/exec.c
index 5557cc9..565d494 100644
--- a/exec.c
+++ b/exec.c
@@ -2444,7 +2444,8 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
uint8_t *buf = b;
g_assert(access_type == MEM_DATA_STORE ||
- access_type == MEM_DATA_LOAD);
+ access_type == MEM_DATA_LOAD ||
+ access_type == MEM_DEBUG_STORE);
while (len > 0) {
page = addr & TARGET_PAGE_MASK;
@@ -2556,7 +2557,8 @@ static MemTxResult address_space_write_continue(AddressSpace *as, hwaddr addr,
MemTxAttrs attrs,
const uint8_t *buf,
int len, hwaddr addr1,
- hwaddr l, MemoryRegion *mr)
+ hwaddr l, MemoryRegion *mr,
+ bool debug)
{
uint8_t *ptr;
uint64_t val;
@@ -2564,7 +2566,15 @@ static MemTxResult address_space_write_continue(AddressSpace *as, hwaddr addr,
bool release_lock = false;
for (;;) {
- if (!memory_access_is_direct(mr, true)) {
+ /*
+ * debug_direct is used to copy the semantics of
+ * cpu_physical_memory_write_rom() which was originally used
+ * to handle writes to memory with GDBStub
+ */
+ const bool debug_direct = (debug && !(memory_region_is_ram(mr) ||
+ memory_region_is_romd(mr)));
+
+ if (!memory_access_is_direct(mr, true) || !debug_direct) {
release_lock |= prepare_mmio_access(mr);
l = memory_access_size(mr, l, addr1);
/* XXX: could force current_cpu to NULL to avoid
@@ -2615,8 +2625,10 @@ static MemTxResult address_space_write_continue(AddressSpace *as, hwaddr addr,
return result;
}
-MemTxResult address_space_write(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
- const void *buf, int len)
+static MemTxResult address_space_write_combined(AddressSpace *as, hwaddr addr,
+ MemTxAttrs attrs,
+ const void *buf, int len,
+ bool debug)
{
hwaddr l;
hwaddr addr1;
@@ -2628,11 +2640,25 @@ MemTxResult address_space_write(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
l = len;
mr = address_space_translate(as, addr, &addr1, &l, true);
result = address_space_write_continue(as, addr, attrs, buf, len,
- addr1, l, mr);
+ addr1, l, mr, debug);
rcu_read_unlock();
}
return result;
+
+}
+
+MemTxResult address_space_write(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
+ const void *buf, int len)
+{
+ return address_space_write_combined(as, addr, attrs, buf, len, false);
+}
+
+static MemTxResult address_space_write_debug(AddressSpace *as, hwaddr addr,
+ MemTxAttrs attrs,
+ const void *buf, int len)
+{
+ return address_space_write_combined(as, addr, attrs, buf, len, true);
}
/* Called within RCU critical section. */
@@ -2734,6 +2760,8 @@ MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
return address_space_write(as, addr, attrs, buf, len);
case MEM_DATA_LOAD:
return address_space_read(as, addr, attrs, buf, len);
+ case MEM_DEBUG_STORE:
+ return address_space_write_debug(as, addr, attrs, buf, len);
default:
abort();
}
@@ -3633,7 +3661,8 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
uint8_t *buf = b;
g_assert(access_type == MEM_DATA_STORE ||
- access_type == MEM_DATA_LOAD);
+ access_type == MEM_DATA_LOAD ||
+ access_type == MEM_DEBUG_STORE);
while (len > 0) {
int asidx;
@@ -3649,14 +3678,10 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
if (l > len)
l = len;
phys_addr += (addr & ~TARGET_PAGE_MASK);
- if (access_type == MEM_DATA_STORE) {
- cpu_physical_memory_write_rom(cpu->cpu_ases[asidx].as,
- phys_addr, buf, l);
- } else {
- address_space_rw(cpu->cpu_ases[asidx].as, phys_addr,
- MEMTXATTRS_UNSPECIFIED,
- buf, l, access_type);
- }
+ address_space_rw(cpu->cpu_ases[asidx].as, phys_addr,
+ MEMTXATTRS_UNSPECIFIED,
+ buf, l, access_type);
+
len -= l;
buf += l;
addr += l;
diff --git a/gdbstub.c b/gdbstub.c
index c215672..03d45f7 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -991,7 +991,7 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
}
hextomem(mem_buf, p, len);
if (target_memory_rw_debug(s->g_cpu, addr, mem_buf, len,
- MEM_DATA_STORE) != 0) {
+ MEM_DEBUG_STORE) != 0) {
put_packet(s, "E14");
} else {
put_packet(s, "OK");
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index b23b4b1..28e30a1 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -63,7 +63,8 @@ typedef uint64_t vaddr;
typedef enum MemoryAccessType {
MEM_DATA_LOAD = 0,
MEM_DATA_STORE = 1,
- MEM_INST_FETCH = 2
+ MEM_INST_FETCH = 2,
+ MEM_DEBUG_STORE = 3,
} MemoryAccessType;
typedef struct CPUWatchpoint CPUWatchpoint;
--
2.5.5
^ permalink raw reply related [flat|nested] 15+ messages in thread