From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37307) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bQI7r-0008R1-Gv for qemu-devel@nongnu.org; Thu, 21 Jul 2016 13:51:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bQI7q-0001zY-Ku for qemu-devel@nongnu.org; Thu, 21 Jul 2016 13:51:11 -0400 Received: from mx1.redhat.com ([209.132.183.28]:42094) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bQI7q-0001zS-EV for qemu-devel@nongnu.org; Thu, 21 Jul 2016 13:51:10 -0400 Date: Thu, 21 Jul 2016 20:51:06 +0300 From: "Michael S. Tsirkin" Message-ID: <1469123413-20809-4-git-send-email-mst@redhat.com> References: <1469123413-20809-1-git-send-email-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1469123413-20809-1-git-send-email-mst@redhat.com> Subject: [Qemu-devel] [PULL v5 03/57] hw/alpha: fix PCI bus initialization List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Marcel Apfelbaum , Mark Cave-Ayland , Richard Henderson From: Marcel Apfelbaum Delay the host-bridge 'realization' until the PCI root bus is attached. Signed-off-by: Marcel Apfelbaum Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Tested-by: Mark Cave-Ayland --- hw/alpha/typhoon.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c index 97721b5..883db13 100644 --- a/hw/alpha/typhoon.c +++ b/hw/alpha/typhoon.c @@ -824,7 +824,6 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, int i; dev = qdev_create(NULL, TYPE_TYPHOON_PCI_HOST_BRIDGE); - qdev_init_nofail(dev); s = TYPHOON_PCI_HOST_BRIDGE(dev); phb = PCI_HOST_BRIDGE(dev); @@ -889,6 +888,7 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, &s->pchip.reg_mem, &s->pchip.reg_io, 0, 64, TYPE_PCI_BUS); phb->bus = b; + qdev_init_nofail(dev); /* Host memory as seen from the PCI side, via the IOMMU. */ memory_region_init_iommu(&s->pchip.iommu, OBJECT(s), &typhoon_iommu_ops, -- MST