From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55926) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bQa4K-00012t-AY for qemu-devel@nongnu.org; Fri, 22 Jul 2016 09:00:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bQa4G-0002Hx-4J for qemu-devel@nongnu.org; Fri, 22 Jul 2016 09:00:43 -0400 Received: from ssl.serverraum.org ([2a01:4f8:130:84d6::1:2]:57071) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bQa4F-0002H1-9L for qemu-devel@nongnu.org; Fri, 22 Jul 2016 09:00:40 -0400 From: Michael Walle Date: Fri, 22 Jul 2016 15:00:08 +0200 Message-Id: <1469192408-21713-1-git-send-email-michael@walle.cc> Subject: [Qemu-devel] [PATCH] target-ppc: set MSR_CM bit for BookE 2.06 MMU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: David Gibson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Michael Walle 64 bit user mode doesn't work for the e5500 core because the MSR_CM bit is not set which enables the 64 bit mode for this MMU model. Memory addresses are truncated to 32 bit, which results in "Invalid data memory access" error messages. Fix it by setting the MSR_CM bit for this MMU model. Signed-off-by: Michael Walle --- target-ppc/translate_init.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 5ecafc7..1ebb143 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -10218,6 +10218,9 @@ static void ppc_cpu_reset(CPUState *s) if (env->mmu_model & POWERPC_MMU_64) { msr |= (1ULL << MSR_SF); } + if (env->mmu_model == POWERPC_MMU_BOOKE206) { + msr |= (1ULL << MSR_CM); + } #endif hreg_store_msr(env, msr, 1); -- 2.1.4