From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net
Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com,
bharata@linux.vnet.ibm.com, aneesh.kumar@linux.vnet.ibm.com
Subject: [Qemu-devel] [PATCH v3 10/15] target-ppc: add cnttzw[.] instruction
Date: Mon, 25 Jul 2016 22:50:35 +0530 [thread overview]
Message-ID: <1469467240-21273-11-git-send-email-nikunj@linux.vnet.ibm.com> (raw)
In-Reply-To: <1469467240-21273-1-git-send-email-nikunj@linux.vnet.ibm.com>
Add ISA3.0: Count trailing zeros word instruction.
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 5 +++++
target-ppc/translate.c | 11 +++++++++++
3 files changed, 17 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 0c29c01..9c79808 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -38,6 +38,7 @@ DEF_HELPER_4(divweu, tl, env, tl, tl, i32)
DEF_HELPER_4(divwe, tl, env, tl, tl, i32)
DEF_HELPER_FLAGS_1(cntlzw, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(cnttzw, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 93e8dfa..02b6df3 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -145,6 +145,11 @@ target_ulong helper_cntlzw(target_ulong t)
return clz32(t);
}
+target_ulong helper_cnttzw(target_ulong t)
+{
+ return ctz32(t);
+}
+
#if defined(TARGET_PPC64)
target_ulong helper_cntlzd(target_ulong t)
{
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index c056320..da94404 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1584,6 +1584,16 @@ static void gen_cntlzw(DisasContext *ctx)
if (unlikely(Rc(ctx->opcode) != 0))
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
+
+/* cnttzw */
+static void gen_cnttzw(DisasContext *ctx)
+{
+ gen_helper_cnttzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
+ if (unlikely(Rc(ctx->opcode) != 0)) {
+ gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
+ }
+}
+
/* eqv & eqv. */
GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
/* extsb & extsb. */
@@ -10058,6 +10068,7 @@ GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
+GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
--
2.7.4
next prev parent reply other threads:[~2016-07-25 17:21 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-25 17:20 [Qemu-devel] [PATCH v3 00/15] POWER9 TCG enablements - part1 Nikunj A Dadhania
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 01/15] target-ppc: Introduce Power9 family Nikunj A Dadhania
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 02/15] target-ppc: Introduce POWER ISA 3.0 flag Nikunj A Dadhania
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 03/15] target-ppc: adding addpcis instruction Nikunj A Dadhania
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 04/15] target-ppc: add cmprb instruction Nikunj A Dadhania
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 05/15] target-ppc: add modulo word operations Nikunj A Dadhania
2016-07-26 0:09 ` Richard Henderson
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 06/15] target-ppc: add modulo dword operations Nikunj A Dadhania
2016-07-26 0:10 ` Richard Henderson
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 07/15] target-ppc: implement branch-less divw[o][.] Nikunj A Dadhania
2016-07-26 0:17 ` Richard Henderson
2016-07-26 1:52 ` Nikunj A Dadhania
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 08/15] target-ppc: implement branch-less divd[o][.] Nikunj A Dadhania
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 09/15] target-ppc: add cnttzd[.] instruction Nikunj A Dadhania
2016-07-25 17:20 ` Nikunj A Dadhania [this message]
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 11/15] target-ppc: add cmpeqb instruction Nikunj A Dadhania
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 12/15] target-ppc: add setb instruction Nikunj A Dadhania
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 13/15] target-ppc: add maddld instruction Nikunj A Dadhania
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 14/15] target-ppc: add maddhd and maddhdu instruction Nikunj A Dadhania
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 15/15] target-ppc: introduce opc4 for Expanded Opcode Nikunj A Dadhania
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