From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net
Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com,
bharata@linux.vnet.ibm.com, aneesh.kumar@linux.vnet.ibm.com
Subject: [Qemu-devel] [PATCH v3 02/15] target-ppc: Introduce POWER ISA 3.0 flag
Date: Mon, 25 Jul 2016 22:50:27 +0530 [thread overview]
Message-ID: <1469467240-21273-3-git-send-email-nikunj@linux.vnet.ibm.com> (raw)
In-Reply-To: <1469467240-21273-1-git-send-email-nikunj@linux.vnet.ibm.com>
This flag will be used for POWER9 instructions.
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/cpu.h | 5 ++++-
target-ppc/translate_init.c | 2 +-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 5fce1ff..c499315 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -2094,6 +2094,8 @@ enum {
PPC2_TM = 0x0000000000020000ULL,
/* Server PM instructgions (ISA 2.06, Book III) */
PPC2_PM_ISA206 = 0x0000000000040000ULL,
+ /* POWER ISA 3.0 */
+ PPC2_ISA300 = 0x0000000000080000ULL,
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
@@ -2101,7 +2103,8 @@ enum {
PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
- PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206)
+ PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
+ PPC2_ISA300)
};
/*****************************************************************************/
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 9f907ee..380b169 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8820,7 +8820,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
- PPC2_TM | PPC2_PM_ISA206;
+ PPC2_TM | PPC2_PM_ISA206 | PPC2_ISA300;
pcc->msr_mask = (1ull << MSR_SF) |
(1ull << MSR_TM) |
(1ull << MSR_VR) |
--
2.7.4
next prev parent reply other threads:[~2016-07-25 17:21 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-25 17:20 [Qemu-devel] [PATCH v3 00/15] POWER9 TCG enablements - part1 Nikunj A Dadhania
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 01/15] target-ppc: Introduce Power9 family Nikunj A Dadhania
2016-07-25 17:20 ` Nikunj A Dadhania [this message]
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 03/15] target-ppc: adding addpcis instruction Nikunj A Dadhania
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 04/15] target-ppc: add cmprb instruction Nikunj A Dadhania
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 05/15] target-ppc: add modulo word operations Nikunj A Dadhania
2016-07-26 0:09 ` Richard Henderson
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 06/15] target-ppc: add modulo dword operations Nikunj A Dadhania
2016-07-26 0:10 ` Richard Henderson
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 07/15] target-ppc: implement branch-less divw[o][.] Nikunj A Dadhania
2016-07-26 0:17 ` Richard Henderson
2016-07-26 1:52 ` Nikunj A Dadhania
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 08/15] target-ppc: implement branch-less divd[o][.] Nikunj A Dadhania
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 09/15] target-ppc: add cnttzd[.] instruction Nikunj A Dadhania
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 10/15] target-ppc: add cnttzw[.] instruction Nikunj A Dadhania
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 11/15] target-ppc: add cmpeqb instruction Nikunj A Dadhania
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 12/15] target-ppc: add setb instruction Nikunj A Dadhania
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 13/15] target-ppc: add maddld instruction Nikunj A Dadhania
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 14/15] target-ppc: add maddhd and maddhdu instruction Nikunj A Dadhania
2016-07-25 17:20 ` [Qemu-devel] [PATCH v3 15/15] target-ppc: introduce opc4 for Expanded Opcode Nikunj A Dadhania
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