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From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: Tue, 26 Jul 2016 07:46:09 +1000
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Subject: Re: [Qemu-devel] TCG problem with cpu_{st,ld}x_data ?
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To: Richard Henderson <rth@twiddle.net>, qemu-devel@nongnu.org
Cc: Paolo Bonzini <pbonzini@redhat.com>, Christian Borntraeger <borntraeger@de.ibm.com>

On Mon, 2016-07-25 at 19:42 +0530, Richard Henderson wrote:
> For some targets, we also restore part of the flags computation with th=
is=C2=A0
> mechanism.=C2=A0 With more trickery, ARM is (intending to?) compute exc=
eption=C2=A0
> syndrome information with this.=C2=A0 As I understand it, this is very =
much akin to=C2=A0
> the PPC gen_set_access_type, so perhaps in future there's some savings =
to be=C2=A0
> had there

Indeed. Another issue we have is generating the opcode bits in DSISR.
Now thankfully for most modern CPUs this is no longer done in HW but at
the moment, I dont like how we call cpu_ldl_code() in powerpc_excp.

Cheers,
Ben.