From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59477) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bRpWP-0007CX-GN for qemu-devel@nongnu.org; Mon, 25 Jul 2016 19:42:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bRpWL-000873-Af for qemu-devel@nongnu.org; Mon, 25 Jul 2016 19:42:52 -0400 Received: from mail-wm0-f67.google.com ([74.125.82.67]:35644) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bRpWL-00086z-4M for qemu-devel@nongnu.org; Mon, 25 Jul 2016 19:42:49 -0400 Received: by mail-wm0-f67.google.com with SMTP id i5so18884854wmg.2 for ; Mon, 25 Jul 2016 16:42:48 -0700 (PDT) From: =?UTF-8?q?Andr=C3=A9=20Draszik?= Date: Tue, 26 Jul 2016 00:42:45 +0100 Message-Id: <1469490165-23915-1-git-send-email-git@andred.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH] target-mips: add 24KEc CPU definition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Leon Alrae Define a new CPU definition supporting 24KEc cores, similar to the existing 24Kc, but with added support for DSP instructions and MIPS16e (and without FPU). Signed-off-by: André Draszik --- target-mips/translate_init.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 39ed5c4..6ae23e4 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -256,6 +256,28 @@ static const mips_def_t mips_defs[] = .mmu_type = MMU_TYPE_R4000, }, { + .name = "24KEc", + .CP0_PRid = 0x00019600, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_CA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSPP) | (0 << CP0C3_VInt), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + /* we have a DSP, but no FPU */ + .CP0_Status_rw_bitmask = 0x1378FF1F, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP, + .mmu_type = MMU_TYPE_R4000, + }, + { .name = "24Kf", .CP0_PRid = 0x00019300, .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | -- 2.8.1