From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53238) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bS11A-0003kp-1O for qemu-devel@nongnu.org; Tue, 26 Jul 2016 07:59:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bS116-0006wZ-Uw for qemu-devel@nongnu.org; Tue, 26 Jul 2016 07:59:24 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:18529) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bS116-0006vN-Kb for qemu-devel@nongnu.org; Tue, 26 Jul 2016 07:59:20 -0400 Received: from pps.filterd (m0098404.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id u6QBrbj6026463 for ; Tue, 26 Jul 2016 07:59:20 -0400 Received: from e28smtp09.in.ibm.com (e28smtp09.in.ibm.com [125.16.236.9]) by mx0a-001b2d01.pphosted.com with ESMTP id 24e1h7e3y6-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Tue, 26 Jul 2016 07:59:19 -0400 Received: from localhost by e28smtp09.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 26 Jul 2016 17:29:16 +0530 From: Nikunj A Dadhania Date: Tue, 26 Jul 2016 17:28:35 +0530 In-Reply-To: <1469534318-5549-1-git-send-email-nikunj@linux.vnet.ibm.com> References: <1469534318-5549-1-git-send-email-nikunj@linux.vnet.ibm.com> Message-Id: <1469534318-5549-13-git-send-email-nikunj@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH v4 12/15] target-ppc: add setb instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com, bharata@linux.vnet.ibm.com, aneesh.kumar@linux.vnet.ibm.com, Vivek Andrew Sha From: Vivek Andrew Sha The CR number is provided in the opcode as - BFA (11:13) Returns: -1 if bit 0 of CR field is set 1 if bit 1 of CR field is set 0 otherwise. Signed-off-by: Vivek Andrew Sha [ reworded commit, used 32bit ops as crf is 32bits ] Signed-off-by: Nikunj A Dadhania Reviewed-by: Richard Henderson --- target-ppc/translate.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 8d56da8..fa1c28c 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -4868,6 +4868,27 @@ static void gen_mtspr(DisasContext *ctx) } } +#if defined(TARGET_PPC64) +/* setb */ +static void gen_setb(DisasContext *ctx) +{ + TCGv_i32 t0 = tcg_temp_new_i32(); + TCGv_i32 t8 = tcg_temp_new_i32(); + TCGv_i32 tm1 = tcg_temp_new_i32(); + int crf = crfS(ctx->opcode); + + tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); + tcg_gen_movi_i32(t8, 8); + tcg_gen_movi_i32(tm1, -1); + tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); + tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); + + tcg_temp_free_i32(t0); + tcg_temp_free_i32(t8); + tcg_temp_free_i32(tm1); +} +#endif + /*** Cache management ***/ /* dcbf */ @@ -10186,6 +10207,7 @@ GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), #if defined(TARGET_PPC64) GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), +GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), #endif GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), -- 2.7.4