From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59309) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bS80y-0006mI-TQ for qemu-devel@nongnu.org; Tue, 26 Jul 2016 15:27:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bS80u-0002je-Ml for qemu-devel@nongnu.org; Tue, 26 Jul 2016 15:27:39 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:57692) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bS80u-0002jL-FQ for qemu-devel@nongnu.org; Tue, 26 Jul 2016 15:27:36 -0400 Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id u6QJOKOM074060 for ; Tue, 26 Jul 2016 15:27:36 -0400 Received: from e23smtp09.au.ibm.com (e23smtp09.au.ibm.com [202.81.31.142]) by mx0a-001b2d01.pphosted.com with ESMTP id 24dsrnwmhv-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Tue, 26 Jul 2016 15:27:35 -0400 Received: from localhost by e23smtp09.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 27 Jul 2016 05:27:33 +1000 From: Nikunj A Dadhania Date: Wed, 27 Jul 2016 00:56:57 +0530 In-Reply-To: <1469561218-3067-1-git-send-email-nikunj@linux.vnet.ibm.com> References: <1469561218-3067-1-git-send-email-nikunj@linux.vnet.ibm.com> Message-Id: <1469561218-3067-6-git-send-email-nikunj@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH RFC v0 5/6] target-ppc: add vsrv instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com, bharata@linux.vnet.ibm.com, aneesh.kumar@linux.vnet.ibm.com, benh@kernel.crashing.org, Vivek Andrew Sha From: Vivek Andrew Sha Adds Vector Shift Right Variable instruction. Signed-off-by: Vivek Andrew Sha Signed-off-by: Nikunj A Dadhania --- target-ppc/helper.h | 1 + target-ppc/int_helper.c | 17 +++++++++++++++++ target-ppc/translate.c | 2 ++ 3 files changed, 20 insertions(+) diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 9703f85..8eada2f 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -211,6 +211,7 @@ DEF_HELPER_3(vslw, void, avr, avr, avr) DEF_HELPER_3(vsld, void, avr, avr, avr) DEF_HELPER_3(vslo, void, avr, avr, avr) DEF_HELPER_3(vsro, void, avr, avr, avr) +DEF_HELPER_3(vsrv, void, avr, avr, avr) DEF_HELPER_3(vslv, void, avr, avr, avr) DEF_HELPER_3(vaddcuw, void, avr, avr, avr) DEF_HELPER_3(vsubcuw, void, avr, avr, avr) diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c index 412398f..f4776f0 100644 --- a/target-ppc/int_helper.c +++ b/target-ppc/int_helper.c @@ -1722,6 +1722,23 @@ void helper_vslv(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) } } +void helper_vsrv(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) +{ + int i; + unsigned int shift, bytes, src[ARRAY_SIZE(r->u8) + 1]; + + src[0] = 0; + for (i = 0; i < ARRAY_SIZE(r->u8); i++) { + src[i + 1] = a->u8[i]; + } + + for (i = 0; i < ARRAY_SIZE(r->u8); i++) { + shift = b->u8[i] & 0x7; /* extract shift value */ + bytes = (src[i] << 8) + src[i + 1]; /* extract adjacent bytes */ + r->u8[i] = (bytes >> shift) & 0xFF; /* shift and store result */ + } +} + void helper_vsldoi(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t shift) { int sh = shift & 0xf; diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 473f21a..3382cd0 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -7457,6 +7457,7 @@ GEN_VXFORM(vsraw, 2, 14); GEN_VXFORM(vsrad, 2, 15); GEN_VXFORM(vslo, 6, 16); GEN_VXFORM(vsro, 6, 17); +GEN_VXFORM(vsrv, 2, 28); GEN_VXFORM(vslv, 2, 29); GEN_VXFORM(vaddcuw, 0, 6); GEN_VXFORM(vsubcuw, 0, 22); @@ -10943,6 +10944,7 @@ GEN_VXFORM(vsraw, 2, 14), GEN_VXFORM_207(vsrad, 2, 15), GEN_VXFORM(vslo, 6, 16), GEN_VXFORM(vsro, 6, 17), +GEN_VXFORM(vsrv, 2, 28), GEN_VXFORM(vslv, 2, 29), GEN_VXFORM(vaddcuw, 0, 6), GEN_VXFORM(vsubcuw, 0, 22), -- 2.7.4