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From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: Wed, 27 Jul 2016 14:02:40 +1000
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Subject: Re: [Qemu-devel] [PATCH 26/32] ppc: Speed up dcbz
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To: David Gibson <david@gibson.dropbear.id.au>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org

On Wed, 2016-07-27 at 12:36 +1000, David Gibson wrote:
> > -=C2=A0=C2=A0=C2=A0 do_dcbz(env, addr, dcbz_size, GETPC());
> > +=C2=A0=C2=A0=C2=A0 /* Try fast path translate */
> > +=C2=A0=C2=A0=C2=A0 haddr =3D tlb_vaddr_to_host(env, addr, MMU_DATA_S=
TORE, env->dmmu_idx);
>=20
> It worries me slightly that this doesn't take any length to verify.=C2=A0=
 I
> guess it's ok in practice, because memory blocks will always be at
> least cache line size aligned.

It's safe ;-)

The translate returns a qemu page size address which is always 4K.

We don't need to verify=C2=A0 because we just aligned the address to the
cache block size which is always smaller than 4k. So we can't
possibly be crossing a page boundary.

(grep for tlb_vaddr_to_host in target-s390 for other examples of use
of tlb_vaddr_to_host).

Cheers,
Ben.