From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38020) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bSmIo-0007Hs-0K for qemu-devel@nongnu.org; Thu, 28 Jul 2016 10:28:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bSmIi-0005mc-8S for qemu-devel@nongnu.org; Thu, 28 Jul 2016 10:28:45 -0400 Received: from 5.mo7.mail-out.ovh.net ([178.32.120.239]:58040) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bSmIi-0005mK-2R for qemu-devel@nongnu.org; Thu, 28 Jul 2016 10:28:40 -0400 Received: from player796.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id 378181000BF9 for ; Thu, 28 Jul 2016 16:28:39 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Thu, 28 Jul 2016 16:28:10 +0200 Message-Id: <1469716099-8975-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v2 0/9] arm: add ast2500 support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Andrew Jeffery , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= The ast2500 soc being very close to the ast2400 soc, the goal of the changes below is to modify the existing platform 'palmetto-bmc' and existing soc 'ast2400' to take into account the small differences and avoid code duplication. This is mostly inspired by the realview platform. First patches rework the 'palmetto-bmc' platform and the 'ast2400' soc models to provide room to other platforms and socs which have a common design. Being able to set the 'silicon-rev' and the cpu model are the primary motivation. The last patches add support for the new ast2500 soc in the required controller (sdmc and scu) and define a new platform for an Aspeed evaluation board. On the ast2500, I am still having a little issue under uboot which sets the vbar doing : mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */ and this is trapped as an undefined instruction by qemu. Looking at hw/arm/helper.c, the VBAR register seems to be defined only for feature ARM_FEATURE_V7 (v7_cp_reginfo). The ast2500 soc uses a arm1176 which defines ARM_FEATURE_EL3 which gives us a VBAR_EL3. According to th specs, the arm1176jzf-s has a Vector Base Address Register. So am I missing something in the board definition or is uboot being too optimistic on the cpu features ? This is confusing for me, some direction would be welcomed :) A part from that, the soc behaves fine. Thanks, Most notable changes in v2 are : - palmetto_bmc.c file rename - SCU macros to define the hardware strapping register=20 C=C3=A9dric Le Goater (9): palmetto-bmc: rename file to aspeed.c palmetto-bmc: add a "silicon-rev" property at the soc level palmetto-bmc: replace palmetto_bmc with aspeed ast2400: use machine cpu_model to initialize the soc cpu palmetto-bmc: add board specific configuration hw/misc: use macros to define hw-strap1 register on Aspeed SOC aspeed: add ast2500 support to scu and sdmc controllers arm: add support for an ast2500 evaluation board palmetto-bmc: remove extra no_sdcard assignement hw/arm/Makefile.objs | 2 +- hw/arm/aspeed.c | 166 +++++++++++++++++++++++++++++++++++++= ++++++ hw/arm/ast2400.c | 21 ++++-- hw/arm/palmetto-bmc.c | 102 -------------------------- hw/misc/aspeed_scu.c | 45 +++++++++++- hw/misc/aspeed_sdmc.c | 1 + include/hw/arm/ast2400.h | 5 ++ include/hw/misc/aspeed_scu.h | 165 +++++++++++++++++++++++++++++++++++++= +++++ 8 files changed, 397 insertions(+), 110 deletions(-) create mode 100644 hw/arm/aspeed.c delete mode 100644 hw/arm/palmetto-bmc.c --=20 2.1.4