[Qemu-devel] [PATCH v2 0/9] arm: add ast2500 support

[Qemu-devel] [PATCH v2 0/9] arm: add ast2500 support

[Cédric Le Goater]

The ast2500 soc being very close to the ast2400 soc, the goal of the
changes below is to modify the existing platform 'palmetto-bmc' and
existing soc 'ast2400' to take into account the small differences and
avoid code duplication. This is mostly inspired by the realview
platform.

First patches rework the 'palmetto-bmc' platform and the 'ast2400' soc
models to provide room to other platforms and socs which have a common
design. Being able to set the 'silicon-rev' and the cpu model are the
primary motivation.

The last patches add support for the new ast2500 soc in the required
controller (sdmc and scu) and define a new platform for an Aspeed
evaluation board.

On the ast2500, I am still having a little issue under uboot which
sets the vbar doing :

	mcr     p15, 0, r0, c12, c0, 0  /* Set VBAR */

and this is trapped as an undefined instruction by qemu.

Looking at hw/arm/helper.c, the VBAR register seems to be defined only
for feature ARM_FEATURE_V7 (v7_cp_reginfo). The ast2500 soc uses a
arm1176 which defines ARM_FEATURE_EL3 which gives us a VBAR_EL3.
According to th specs, the arm1176jzf-s has a Vector Base Address
Register. So am I missing something in the board definition or is
uboot being too optimistic on the cpu features ? This is confusing for
me, some direction would be welcomed :)

A part from that, the soc behaves fine.

Thanks,

Most notable changes in v2 are :

  - palmetto_bmc.c file rename
  - SCU macros to define the hardware strapping register 

Cédric Le Goater (9):
  palmetto-bmc: rename file to aspeed.c
  palmetto-bmc: add a "silicon-rev" property at the soc level
  palmetto-bmc: replace palmetto_bmc with aspeed
  ast2400: use machine cpu_model to initialize the soc cpu
  palmetto-bmc: add board specific configuration
  hw/misc: use macros to define hw-strap1 register on Aspeed SOC
  aspeed: add ast2500 support to scu and sdmc controllers
  arm: add support for an ast2500 evaluation board
  palmetto-bmc: remove extra no_sdcard assignement

 hw/arm/Makefile.objs         |   2 +-
 hw/arm/aspeed.c              | 166 +++++++++++++++++++++++++++++++++++++++++++
 hw/arm/ast2400.c             |  21 ++++--
 hw/arm/palmetto-bmc.c        | 102 --------------------------
 hw/misc/aspeed_scu.c         |  45 +++++++++++-
 hw/misc/aspeed_sdmc.c        |   1 +
 include/hw/arm/ast2400.h     |   5 ++
 include/hw/misc/aspeed_scu.h | 165 ++++++++++++++++++++++++++++++++++++++++++
 8 files changed, 397 insertions(+), 110 deletions(-)
 create mode 100644 hw/arm/aspeed.c
 delete mode 100644 hw/arm/palmetto-bmc.c

-- 
2.1.4

[Qemu-devel] [PATCH v2 1/9] palmetto-bmc: rename file to aspeed.c

[Cédric Le Goater]

We plan to add more Aspeed platform to this file. Let's rename it to a
more generic name. There are no changes in the code.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/Makefile.objs  |   2 +-
 hw/arm/aspeed.c       | 102 ++++++++++++++++++++++++++++++++++++++++++++++++++
 hw/arm/palmetto-bmc.c | 102 --------------------------------------------------
 3 files changed, 103 insertions(+), 103 deletions(-)
 create mode 100644 hw/arm/aspeed.c
 delete mode 100644 hw/arm/palmetto-bmc.c

diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 12764ef2b719..8cc700231b30 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -17,4 +17,4 @@ obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o xlnx-ep108.o
 obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
 obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
 obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
-obj-$(CONFIG_ASPEED_SOC) += ast2400.o palmetto-bmc.o
+obj-$(CONFIG_ASPEED_SOC) += ast2400.o aspeed.o
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
new file mode 100644
index 000000000000..54e29a865d88
--- /dev/null
+++ b/hw/arm/aspeed.c
@@ -0,0 +1,102 @@
+/*
+ * OpenPOWER Palmetto BMC
+ *
+ * Andrew Jeffery <andrew@aj.id.au>
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later.  See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "cpu.h"
+#include "exec/address-spaces.h"
+#include "hw/arm/arm.h"
+#include "hw/arm/ast2400.h"
+#include "hw/boards.h"
+#include "qemu/log.h"
+#include "sysemu/block-backend.h"
+#include "sysemu/blockdev.h"
+
+static struct arm_boot_info palmetto_bmc_binfo = {
+    .loader_start = AST2400_SDRAM_BASE,
+    .board_id = 0,
+    .nb_cpus = 1,
+};
+
+typedef struct PalmettoBMCState {
+    AST2400State soc;
+    MemoryRegion ram;
+} PalmettoBMCState;
+
+static void palmetto_bmc_init_flashes(AspeedSMCState *s, const char *flashtype,
+                                      Error **errp)
+{
+    int i ;
+
+    for (i = 0; i < s->num_cs; ++i) {
+        AspeedSMCFlash *fl = &s->flashes[i];
+        DriveInfo *dinfo = drive_get_next(IF_MTD);
+        qemu_irq cs_line;
+
+        /*
+         * FIXME: check that we are not using a flash module exceeding
+         * the controller segment size
+         */
+        fl->flash = ssi_create_slave_no_init(s->spi, flashtype);
+        if (dinfo) {
+            qdev_prop_set_drive(fl->flash, "drive", blk_by_legacy_dinfo(dinfo),
+                                errp);
+        }
+        qdev_init_nofail(fl->flash);
+
+        cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0);
+        sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
+    }
+}
+
+static void palmetto_bmc_init(MachineState *machine)
+{
+    PalmettoBMCState *bmc;
+
+    bmc = g_new0(PalmettoBMCState, 1);
+    object_initialize(&bmc->soc, (sizeof(bmc->soc)), TYPE_AST2400);
+    object_property_add_child(OBJECT(machine), "soc", OBJECT(&bmc->soc),
+                              &error_abort);
+
+    memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size);
+    memory_region_add_subregion(get_system_memory(), AST2400_SDRAM_BASE,
+                                &bmc->ram);
+    object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),
+                                   &error_abort);
+    object_property_set_int(OBJECT(&bmc->soc), 0x120CE416, "hw-strap1",
+                            &error_abort);
+    object_property_set_bool(OBJECT(&bmc->soc), true, "realized",
+                             &error_abort);
+
+    palmetto_bmc_init_flashes(&bmc->soc.smc, "n25q256a", &error_abort);
+    palmetto_bmc_init_flashes(&bmc->soc.spi, "mx25l25635e", &error_abort);
+
+    palmetto_bmc_binfo.kernel_filename = machine->kernel_filename;
+    palmetto_bmc_binfo.initrd_filename = machine->initrd_filename;
+    palmetto_bmc_binfo.kernel_cmdline = machine->kernel_cmdline;
+    palmetto_bmc_binfo.ram_size = ram_size;
+    arm_load_kernel(ARM_CPU(first_cpu), &palmetto_bmc_binfo);
+}
+
+static void palmetto_bmc_machine_init(MachineClass *mc)
+{
+    mc->desc = "OpenPOWER Palmetto BMC";
+    mc->init = palmetto_bmc_init;
+    mc->max_cpus = 1;
+    mc->no_sdcard = 1;
+    mc->no_floppy = 1;
+    mc->no_cdrom = 1;
+    mc->no_sdcard = 1;
+    mc->no_parallel = 1;
+}
+
+DEFINE_MACHINE("palmetto-bmc", palmetto_bmc_machine_init);
diff --git a/hw/arm/palmetto-bmc.c b/hw/arm/palmetto-bmc.c
deleted file mode 100644
index 54e29a865d88..000000000000
--- a/hw/arm/palmetto-bmc.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * OpenPOWER Palmetto BMC
- *
- * Andrew Jeffery <andrew@aj.id.au>
- *
- * Copyright 2016 IBM Corp.
- *
- * This code is licensed under the GPL version 2 or later.  See
- * the COPYING file in the top-level directory.
- */
-
-#include "qemu/osdep.h"
-#include "qapi/error.h"
-#include "qemu-common.h"
-#include "cpu.h"
-#include "exec/address-spaces.h"
-#include "hw/arm/arm.h"
-#include "hw/arm/ast2400.h"
-#include "hw/boards.h"
-#include "qemu/log.h"
-#include "sysemu/block-backend.h"
-#include "sysemu/blockdev.h"
-
-static struct arm_boot_info palmetto_bmc_binfo = {
-    .loader_start = AST2400_SDRAM_BASE,
-    .board_id = 0,
-    .nb_cpus = 1,
-};
-
-typedef struct PalmettoBMCState {
-    AST2400State soc;
-    MemoryRegion ram;
-} PalmettoBMCState;
-
-static void palmetto_bmc_init_flashes(AspeedSMCState *s, const char *flashtype,
-                                      Error **errp)
-{
-    int i ;
-
-    for (i = 0; i < s->num_cs; ++i) {
-        AspeedSMCFlash *fl = &s->flashes[i];
-        DriveInfo *dinfo = drive_get_next(IF_MTD);
-        qemu_irq cs_line;
-
-        /*
-         * FIXME: check that we are not using a flash module exceeding
-         * the controller segment size
-         */
-        fl->flash = ssi_create_slave_no_init(s->spi, flashtype);
-        if (dinfo) {
-            qdev_prop_set_drive(fl->flash, "drive", blk_by_legacy_dinfo(dinfo),
-                                errp);
-        }
-        qdev_init_nofail(fl->flash);
-
-        cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0);
-        sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
-    }
-}
-
-static void palmetto_bmc_init(MachineState *machine)
-{
-    PalmettoBMCState *bmc;
-
-    bmc = g_new0(PalmettoBMCState, 1);
-    object_initialize(&bmc->soc, (sizeof(bmc->soc)), TYPE_AST2400);
-    object_property_add_child(OBJECT(machine), "soc", OBJECT(&bmc->soc),
-                              &error_abort);
-
-    memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size);
-    memory_region_add_subregion(get_system_memory(), AST2400_SDRAM_BASE,
-                                &bmc->ram);
-    object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),
-                                   &error_abort);
-    object_property_set_int(OBJECT(&bmc->soc), 0x120CE416, "hw-strap1",
-                            &error_abort);
-    object_property_set_bool(OBJECT(&bmc->soc), true, "realized",
-                             &error_abort);
-
-    palmetto_bmc_init_flashes(&bmc->soc.smc, "n25q256a", &error_abort);
-    palmetto_bmc_init_flashes(&bmc->soc.spi, "mx25l25635e", &error_abort);
-
-    palmetto_bmc_binfo.kernel_filename = machine->kernel_filename;
-    palmetto_bmc_binfo.initrd_filename = machine->initrd_filename;
-    palmetto_bmc_binfo.kernel_cmdline = machine->kernel_cmdline;
-    palmetto_bmc_binfo.ram_size = ram_size;
-    arm_load_kernel(ARM_CPU(first_cpu), &palmetto_bmc_binfo);
-}
-
-static void palmetto_bmc_machine_init(MachineClass *mc)
-{
-    mc->desc = "OpenPOWER Palmetto BMC";
-    mc->init = palmetto_bmc_init;
-    mc->max_cpus = 1;
-    mc->no_sdcard = 1;
-    mc->no_floppy = 1;
-    mc->no_cdrom = 1;
-    mc->no_sdcard = 1;
-    mc->no_parallel = 1;
-}
-
-DEFINE_MACHINE("palmetto-bmc", palmetto_bmc_machine_init);
-- 
2.1.4

[Qemu-devel] [PATCH v2 2/9] palmetto-bmc: add a "silicon-rev" property at the soc level

[Cédric Le Goater]

The SCU controler holds the board revision number in its 0x7C
register. Let's use an alias to link a "silicon-rev" property of the
soc to the "silicon-rev" property of the SCU controler.

The SDMC controler "silicon-rev" property is derived from the SCU one
at realize time. I did not find a better way to handle this part.
Links and aliases being a one-to-one relation, I could not use one of
them. I might wrong though.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed.c  |  2 ++
 hw/arm/ast2400.c | 18 +++++++++++++-----
 2 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 54e29a865d88..1ee13d578899 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -74,6 +74,8 @@ static void palmetto_bmc_init(MachineState *machine)
                                    &error_abort);
     object_property_set_int(OBJECT(&bmc->soc), 0x120CE416, "hw-strap1",
                             &error_abort);
+    object_property_set_int(OBJECT(&bmc->soc), AST2400_A0_SILICON_REV,
+                            "silicon-rev", &error_abort);
     object_property_set_bool(OBJECT(&bmc->soc), true, "realized",
                              &error_abort);
 
diff --git a/hw/arm/ast2400.c b/hw/arm/ast2400.c
index 136bf6464e1d..fa535065f765 100644
--- a/hw/arm/ast2400.c
+++ b/hw/arm/ast2400.c
@@ -84,8 +84,8 @@ static void ast2400_init(Object *obj)
     object_initialize(&s->scu, sizeof(s->scu), TYPE_ASPEED_SCU);
     object_property_add_child(obj, "scu", OBJECT(&s->scu), NULL);
     qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());
-    qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
-                         AST2400_A0_SILICON_REV);
+    object_property_add_alias(obj, "silicon-rev", OBJECT(&s->scu),
+                              "silicon-rev", &error_abort);
     object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
                               "hw-strap1", &error_abort);
     object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
@@ -102,8 +102,6 @@ static void ast2400_init(Object *obj)
     object_initialize(&s->sdmc, sizeof(s->sdmc), TYPE_ASPEED_SDMC);
     object_property_add_child(obj, "sdmc", OBJECT(&s->sdmc), NULL);
     qdev_set_parent_bus(DEVICE(&s->sdmc), sysbus_get_default());
-    qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev",
-                         AST2400_A0_SILICON_REV);
 }
 
 static void ast2400_realize(DeviceState *dev, Error **errp)
@@ -111,6 +109,7 @@ static void ast2400_realize(DeviceState *dev, Error **errp)
     int i;
     AST2400State *s = AST2400(dev);
     Error *err = NULL, *local_err = NULL;
+    uint32_t silicon_rev;
 
     /* IO space */
     memory_region_init_io(&s->iomem, NULL, &ast2400_io_ops, NULL,
@@ -192,7 +191,16 @@ static void ast2400_realize(DeviceState *dev, Error **errp)
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 1, AST2400_SPI_FLASH_BASE);
 
     /* SDMC - SDRAM Memory Controller */
-    object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
+    silicon_rev = (uint32_t)
+        object_property_get_int(OBJECT(&s->scu), "silicon-rev", &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+
+    object_property_set_int(OBJECT(&s->sdmc), silicon_rev, "silicon-rev", &err);
+    object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &local_err);
+    error_propagate(&err, local_err);
     if (err) {
         error_propagate(errp, err);
         return;
-- 
2.1.4

[Qemu-devel] [PATCH v2 3/9] palmetto-bmc: replace palmetto_bmc with aspeed

[Cédric Le Goater]

This is mostly a name replacement to prepare ground for other socs
specificities. It also adds a specific TypeInfo struct for the
palmetto_bmc board with a custom initialization for the same reason.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed.c | 54 ++++++++++++++++++++++++++++++++++++------------------
 1 file changed, 36 insertions(+), 18 deletions(-)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 1ee13d578899..f80a15733864 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -21,19 +21,19 @@
 #include "sysemu/block-backend.h"
 #include "sysemu/blockdev.h"
 
-static struct arm_boot_info palmetto_bmc_binfo = {
+static struct arm_boot_info aspeed_binfo = {
     .loader_start = AST2400_SDRAM_BASE,
     .board_id = 0,
     .nb_cpus = 1,
 };
 
-typedef struct PalmettoBMCState {
+typedef struct AspeedBoardState {
     AST2400State soc;
     MemoryRegion ram;
-} PalmettoBMCState;
+} AspeedBoardState;
 
-static void palmetto_bmc_init_flashes(AspeedSMCState *s, const char *flashtype,
-                                      Error **errp)
+static void aspeed_init_flashes(AspeedSMCState *s, const char *flashtype,
+                                Error **errp)
 {
     int i ;
 
@@ -58,11 +58,11 @@ static void palmetto_bmc_init_flashes(AspeedSMCState *s, const char *flashtype,
     }
 }
 
-static void palmetto_bmc_init(MachineState *machine)
+static void aspeed_init(MachineState *machine)
 {
-    PalmettoBMCState *bmc;
+    AspeedBoardState *bmc;
 
-    bmc = g_new0(PalmettoBMCState, 1);
+    bmc = g_new0(AspeedBoardState, 1);
     object_initialize(&bmc->soc, (sizeof(bmc->soc)), TYPE_AST2400);
     object_property_add_child(OBJECT(machine), "soc", OBJECT(&bmc->soc),
                               &error_abort);
@@ -79,19 +79,26 @@ static void palmetto_bmc_init(MachineState *machine)
     object_property_set_bool(OBJECT(&bmc->soc), true, "realized",
                              &error_abort);
 
-    palmetto_bmc_init_flashes(&bmc->soc.smc, "n25q256a", &error_abort);
-    palmetto_bmc_init_flashes(&bmc->soc.spi, "mx25l25635e", &error_abort);
+    aspeed_init_flashes(&bmc->soc.smc, "n25q256a", &error_abort);
+    aspeed_init_flashes(&bmc->soc.spi, "mx25l25635e", &error_abort);
+
+    aspeed_binfo.kernel_filename = machine->kernel_filename;
+    aspeed_binfo.initrd_filename = machine->initrd_filename;
+    aspeed_binfo.kernel_cmdline = machine->kernel_cmdline;
+    aspeed_binfo.ram_size = ram_size;
+    arm_load_kernel(ARM_CPU(first_cpu), &aspeed_binfo);
+}
 
-    palmetto_bmc_binfo.kernel_filename = machine->kernel_filename;
-    palmetto_bmc_binfo.initrd_filename = machine->initrd_filename;
-    palmetto_bmc_binfo.kernel_cmdline = machine->kernel_cmdline;
-    palmetto_bmc_binfo.ram_size = ram_size;
-    arm_load_kernel(ARM_CPU(first_cpu), &palmetto_bmc_binfo);
+static void palmetto_bmc_init(MachineState *machine)
+{
+    aspeed_init(machine);
 }
 
-static void palmetto_bmc_machine_init(MachineClass *mc)
+static void palmetto_bmc_class_init(ObjectClass *oc, void *data)
 {
-    mc->desc = "OpenPOWER Palmetto BMC";
+    MachineClass *mc = MACHINE_CLASS(oc);
+
+    mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
     mc->init = palmetto_bmc_init;
     mc->max_cpus = 1;
     mc->no_sdcard = 1;
@@ -101,4 +108,15 @@ static void palmetto_bmc_machine_init(MachineClass *mc)
     mc->no_parallel = 1;
 }
 
-DEFINE_MACHINE("palmetto-bmc", palmetto_bmc_machine_init);
+static const TypeInfo palmetto_bmc_type = {
+    .name = MACHINE_TYPE_NAME("palmetto-bmc"),
+    .parent = TYPE_MACHINE,
+    .class_init = palmetto_bmc_class_init,
+};
+
+static void aspeed_machine_init(void)
+{
+    type_register_static(&palmetto_bmc_type);
+}
+
+type_init(aspeed_machine_init)
-- 
2.1.4

[Qemu-devel] [PATCH v2 4/9] ast2400: use machine cpu_model to initialize the soc cpu

[Cédric Le Goater]

It will be easier to specify a different cpu for other soc derived
from the ast2400 soc.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---

 Change since v1:

 - remove check on cpu_model. 

 hw/arm/aspeed.c  | 1 +
 hw/arm/ast2400.c | 3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index f80a15733864..8a3ff5568575 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -91,6 +91,7 @@ static void aspeed_init(MachineState *machine)
 
 static void palmetto_bmc_init(MachineState *machine)
 {
+    machine->cpu_model = "arm926";
     aspeed_init(machine);
 }
 
diff --git a/hw/arm/ast2400.c b/hw/arm/ast2400.c
index fa535065f765..84f3b444db09 100644
--- a/hw/arm/ast2400.c
+++ b/hw/arm/ast2400.c
@@ -15,6 +15,7 @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "exec/address-spaces.h"
+#include "hw/boards.h"
 #include "hw/arm/ast2400.h"
 #include "hw/char/serial.h"
 #include "qemu/log.h"
@@ -67,7 +68,7 @@ static void ast2400_init(Object *obj)
 {
     AST2400State *s = AST2400(obj);
 
-    s->cpu = cpu_arm_init("arm926");
+    s->cpu = cpu_arm_init(current_machine->cpu_model);
 
     object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);
     object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);
-- 
2.1.4

[Qemu-devel] [PATCH v2 5/9] palmetto-bmc: add board specific configuration

[Cédric Le Goater]

aspeed_init() now uses a board identifier to customize some values
specific to the board, ram base, board revision number, etc.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---

 Changes since v1:

 - changed aspeed_init() prototype to use a 'const AspeedBoardConfig *'
 - fixed white space issues
 
 hw/arm/aspeed.c | 31 +++++++++++++++++++++++--------
 1 file changed, 23 insertions(+), 8 deletions(-)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 8a3ff5568575..80be55ab293f 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -22,8 +22,6 @@
 #include "sysemu/blockdev.h"
 
 static struct arm_boot_info aspeed_binfo = {
-    .loader_start = AST2400_SDRAM_BASE,
-    .board_id = 0,
     .nb_cpus = 1,
 };
 
@@ -32,6 +30,21 @@ typedef struct AspeedBoardState {
     MemoryRegion ram;
 } AspeedBoardState;
 
+typedef struct AspeedBoardConfig {
+    uint32_t hw_strap1;
+    uint32_t silicon_rev;
+    hwaddr sdram_base;
+} AspeedBoardConfig;
+
+enum {
+    PALMETTO_BMC
+};
+
+static const AspeedBoardConfig aspeed_boards[] = {
+    [PALMETTO_BMC] = { 0x120CE416, AST2400_A0_SILICON_REV,
+                       AST2400_SDRAM_BASE },
+};
+
 static void aspeed_init_flashes(AspeedSMCState *s, const char *flashtype,
                                 Error **errp)
 {
@@ -58,7 +71,7 @@ static void aspeed_init_flashes(AspeedSMCState *s, const char *flashtype,
     }
 }
 
-static void aspeed_init(MachineState *machine)
+static void aspeed_init(MachineState *machine, const AspeedBoardConfig *cfg)
 {
     AspeedBoardState *bmc;
 
@@ -68,13 +81,13 @@ static void aspeed_init(MachineState *machine)
                               &error_abort);
 
     memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size);
-    memory_region_add_subregion(get_system_memory(), AST2400_SDRAM_BASE,
+    memory_region_add_subregion(get_system_memory(), cfg->sdram_base,
                                 &bmc->ram);
     object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),
                                    &error_abort);
-    object_property_set_int(OBJECT(&bmc->soc), 0x120CE416, "hw-strap1",
-                            &error_abort);
-    object_property_set_int(OBJECT(&bmc->soc), AST2400_A0_SILICON_REV,
+    object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap1,
+                            "hw-strap1", &error_abort);
+    object_property_set_int(OBJECT(&bmc->soc), cfg->silicon_rev,
                             "silicon-rev", &error_abort);
     object_property_set_bool(OBJECT(&bmc->soc), true, "realized",
                              &error_abort);
@@ -86,13 +99,15 @@ static void aspeed_init(MachineState *machine)
     aspeed_binfo.initrd_filename = machine->initrd_filename;
     aspeed_binfo.kernel_cmdline = machine->kernel_cmdline;
     aspeed_binfo.ram_size = ram_size;
+    aspeed_binfo.loader_start = cfg->sdram_base,
+    aspeed_binfo.board_id = cfg->silicon_rev,
     arm_load_kernel(ARM_CPU(first_cpu), &aspeed_binfo);
 }
 
 static void palmetto_bmc_init(MachineState *machine)
 {
     machine->cpu_model = "arm926";
-    aspeed_init(machine);
+    aspeed_init(machine, &aspeed_boards[PALMETTO_BMC]);
 }
 
 static void palmetto_bmc_class_init(ObjectClass *oc, void *data)
-- 
2.1.4

[Qemu-devel] [PATCH v2 6/9] hw/misc: use macros to define hw-strap1 register on Aspeed SOC

[Cédric Le Goater]

This gives some explanation behind the magic number 0x120CE416.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed.c              |   2 +-
 include/hw/misc/aspeed_scu.h | 109 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 110 insertions(+), 1 deletion(-)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 80be55ab293f..b5d34a3a0367 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -41,7 +41,7 @@ enum {
 };
 
 static const AspeedBoardConfig aspeed_boards[] = {
-    [PALMETTO_BMC] = { 0x120CE416, AST2400_A0_SILICON_REV,
+    [PALMETTO_BMC] = { AST2400_HW_STRAP1, AST2400_A0_SILICON_REV,
                        AST2400_SDRAM_BASE },
 };
 
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index fdfd982288f2..dfc3e023f3ba 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -36,4 +36,113 @@ typedef struct AspeedSCUState {
 
 extern bool is_supported_silicon_rev(uint32_t silicon_rev);
 
+/*
+ * Hardware strapping register definition
+ *
+ * Extracted from Aspeed SDK v00.03.21. A couple of fixes and some
+ * extra bit definitions were added.
+ *
+ * Original header file :
+ */
+
+/* arch/arm/mach-aspeed/include/mach/regs-scu.h
+ *
+ * Copyright (C) 2012-2020  ASPEED Technology Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *   History      :
+ *    1. 2012/12/29 Ryan Chen Create
+ */
+#define SCU_HW_STRAP_SW_DEFINE(x)          (x << 29)
+#define SCU_HW_STRAP_SW_DEFINE_MASK        (0x7 << 29)
+
+#define SCU_HW_STRAP_DRAM_SIZE(x)          (x << 27)
+#define SCU_HW_STRAP_DRAM_SIZE_MASK        (0x3 << 27)
+#define     DRAM_SIZE_64MB                     0
+#define     DRAM_SIZE_128MB                    1
+#define     DRAM_SIZE_256MB                    2
+#define     DRAM_SIZE_512MB                    3
+
+#define SCU_HW_STRAP_DRAM_CONFIG(x)        (x << 24)
+#define SCU_HW_STRAP_DRAM_CONFIG_MASK      (0x7 << 24)
+
+#define SCU_HW_STRAP_GPIOE_PT_EN           (0x1 << 22)
+#define SCU_HW_STRAP_GPIOD_PT_EN           (0x1 << 21)
+#define SCU_HW_STRAP_LPC_DEC_SUPER_IO      (0x1 << 20)
+#define SCU_HW_STRAP_ACPI_DIS              (0x1 << 19)
+
+/* bit 23, 18 [1,0] */
+#define SCU_HW_STRAP_SET_CLK_SOURCE(x)     ((((x & 0x3) >> 1) << 23) | \
+                                            ((x & 0x1) << 18))
+#define SCU_HW_STRAP_GET_CLK_SOURCE(x)     ((((x >> 23) & 0x1) << 1) |  \
+                                            ((x >> 18) & 0x1))
+#define SCU_HW_STRAP_CLK_SOURCE_MASK       ((0x1 << 23) | (0x1 << 18))
+#define     CLK_25M_IN                         (0x1 << 23)
+#define     CLK_24M_IN                         0
+#define     CLK_48M_IN                         1
+#define     CLK_25M_IN_24M_USB_CKI             2
+#define     CLK_25M_IN_48M_USB_CKI             3
+
+#define SCU_HW_STRAP_2ND_BOOT_WDT          (0x1 << 17)
+#define SCU_HW_STRAP_SUPER_IO_CONFIG       (0x1 << 16)
+#define SCU_HW_STRAP_VGA_CLASS_CODE        (0x1 << 15)
+#define SCU_HW_STRAP_LPC_RESET_PIN         (0x1 << 14)
+
+#define SCU_HW_STRAP_SPI_MODE(x)           (x << 12)
+#define SCU_HW_STRAP_SPI_MODE_MASK         (0x3 << 12)
+#define     SCU_HW_STRAP_SPI_DIS               0
+#define     SCU_HW_STRAP_SPI_MASTER            1
+#define     SCU_HW_STRAP_SPI_M_S_EN            2
+#define     SCU_HW_STRAP_SPI_PASS_THROUGH      3
+
+#define SCU_HW_STRAP_SET_CPU_AHB_RATIO(x)  (x << 10)
+#define SCU_HW_STRAP_GET_CPU_AHB_RATIO(x)  ((x >> 10) & 3)
+#define SCU_HW_STRAP_CPU_AHB_RATIO_MASK    (0x3 << 10)
+#define     CPU_AHB_RATIO_1_1                  0
+#define     CPU_AHB_RATIO_2_1                  1
+#define     CPU_AHB_RATIO_4_1                  2
+#define     CPU_AHB_RATIO_3_1                  3
+
+#define SCU_HW_STRAP_GET_H_PLL_CLK(x)      ((x >> 8) & 0x3)
+#define SCU_HW_STRAP_H_PLL_CLK_MASK        (0x3 << 8)
+#define     CPU_384MHZ                         0
+#define     CPU_360MHZ                         1
+#define     CPU_336MHZ                         2
+#define     CPU_408MHZ                         3
+
+#define SCU_HW_STRAP_MAC1_RGMII            (0x1 << 7)
+#define SCU_HW_STRAP_MAC0_RGMII            (0x1 << 6)
+#define SCU_HW_STRAP_VGA_BIOS_ROM          (0x1 << 5)
+#define SCU_HW_STRAP_SPI_WIDTH             (0x1 << 4)
+
+#define SCU_HW_STRAP_VGA_SIZE_GET(x)       ((x >> 2) & 0x3)
+#define SCU_HW_STRAP_VGA_MASK              (0x3 << 2)
+#define SCU_HW_STRAP_VGA_SIZE_SET(x)       (x << 2)
+#define     VGA_8M_DRAM                        0
+#define     VGA_16M_DRAM                       1
+#define     VGA_32M_DRAM                       2
+#define     VGA_64M_DRAM                       3
+
+#define SCU_HW_STRAP_BOOT_MODE(x)          (x)
+#define     NOR_BOOT                           0
+#define     NAND_BOOT                          1
+#define     SPI_BOOT                           2
+#define     DIS_BOOT                           3
+
+#define AST2400_HW_STRAP1 (                                             \
+        SCU_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) |                       \
+        SCU_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) |       \
+        SCU_HW_STRAP_ACPI_DIS |                                         \
+        SCU_HW_STRAP_SET_CLK_SOURCE(CLK_48M_IN) |                       \
+        SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
+        SCU_HW_STRAP_LPC_RESET_PIN |                                    \
+        SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) |                \
+        SCU_HW_STRAP_SET_CPU_AHB_RATIO(CPU_AHB_RATIO_2_1) |             \
+        SCU_HW_STRAP_SPI_WIDTH |                                        \
+        SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
+        SCU_HW_STRAP_BOOT_MODE(SPI_BOOT))
+
 #endif /* ASPEED_SCU_H */
-- 
2.1.4

[Qemu-devel] [PATCH v2 7/9] aspeed: add ast2500 support to scu and sdmc controllers

[Cédric Le Goater]

Based on previous work done by Andrew Jeffery <andrew@aj.id.au>.

The ast2500 eval board has a hardware strapping register value of
0xF100C2E6 which we use for a definition of AST2500_HW_STRAP1 below.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---

 Andrew,
 
 I did not add your 'Reviewed-by' because of the changes below.

 Changes since v1:

 - added Hardware strapping register definition for soc AST2500

 hw/misc/aspeed_scu.c         | 45 ++++++++++++++++++++++++++++++++++-
 hw/misc/aspeed_sdmc.c        |  1 +
 include/hw/misc/aspeed_scu.h | 56 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 101 insertions(+), 1 deletion(-)

diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index c7e2c8263f55..6dd7e1085420 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -120,6 +120,41 @@ static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = {
      [BMC_DEV_ID]      = 0x00002402U
 };
 
+/* SCU70 bit 23: 0 24Mhz. bit 11:9: 0b001 AXI:ABH ratio 2:1 */
+/* AST2500 revision A1 */
+
+static const uint32_t ast2500_a1_resets[ASPEED_SCU_NR_REGS] = {
+     [SYS_RST_CTRL]    = 0xFFCFFEDCU,
+     [CLK_SEL]         = 0xF3F40000U,
+     [CLK_STOP_CTRL]   = 0x19FC3E8BU,
+     [D2PLL_PARAM]     = 0x00026108U,
+     [MPLL_PARAM]      = 0x00030291U,
+     [HPLL_PARAM]      = 0x93000400U,
+     [MISC_CTRL1]      = 0x00000010U,
+     [PCI_CTRL1]       = 0x20001A03U,
+     [PCI_CTRL2]       = 0x20001A03U,
+     [PCI_CTRL3]       = 0x04000030U,
+     [SYS_RST_STATUS]  = 0x00000001U,
+     [SOC_SCRATCH1]    = 0x000000C0U, /* SoC completed DRAM init */
+     [MISC_CTRL2]      = 0x00000023U,
+     [RNG_CTRL]        = 0x0000000EU,
+     [PINMUX_CTRL2]    = 0x0000F000U,
+     [PINMUX_CTRL3]    = 0x03000000U,
+     [PINMUX_CTRL4]    = 0x00000000U,
+     [PINMUX_CTRL5]    = 0x0000A000U,
+     [WDT_RST_CTRL]    = 0x023FFFF3U,
+     [PINMUX_CTRL8]    = 0xFFFF0000U,
+     [PINMUX_CTRL9]    = 0x000FFFFFU,
+     [FREE_CNTR4]      = 0x000000FFU,
+     [FREE_CNTR4_EXT]  = 0x000000FFU,
+     [CPU2_BASE_SEG1]  = 0x80000000U,
+     [CPU2_BASE_SEG4]  = 0x1E600000U,
+     [CPU2_BASE_SEG5]  = 0xC0000000U,
+     [UART_HPLL_CLK]   = 0x00001903U,
+     [PCIE_CTRL]       = 0x0000007BU,
+     [BMC_DEV_ID]      = 0x00002402U
+};
+
 static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
 {
     AspeedSCUState *s = ASPEED_SCU(opaque);
@@ -198,6 +233,10 @@ static void aspeed_scu_reset(DeviceState *dev)
     case AST2400_A0_SILICON_REV:
         reset = ast2400_a0_resets;
         break;
+    case AST2500_A0_SILICON_REV:
+    case AST2500_A1_SILICON_REV:
+        reset = ast2500_a1_resets;
+        break;
     default:
         g_assert_not_reached();
     }
@@ -208,7 +247,11 @@ static void aspeed_scu_reset(DeviceState *dev)
     s->regs[HW_STRAP2] = s->hw_strap2;
 }
 
-static uint32_t aspeed_silicon_revs[] = { AST2400_A0_SILICON_REV, };
+static uint32_t aspeed_silicon_revs[] = {
+    AST2400_A0_SILICON_REV,
+    AST2500_A0_SILICON_REV,
+    AST2500_A1_SILICON_REV
+};
 
 bool is_supported_silicon_rev(uint32_t silicon_rev)
 {
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index 6cc0301a6331..621d166890fa 100644
--- a/hw/misc/aspeed_sdmc.c
+++ b/hw/misc/aspeed_sdmc.c
@@ -196,6 +196,7 @@ static void aspeed_sdmc_reset(DeviceState *dev)
         break;
 
     case AST2500_A0_SILICON_REV:
+    case AST2500_A1_SILICON_REV:
         s->regs[R_CONF] |=
             ASPEED_SDMC_HW_VERSION(1) |
             ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index dfc3e023f3ba..d79e2214457d 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -33,6 +33,7 @@ typedef struct AspeedSCUState {
 
 #define AST2400_A0_SILICON_REV   0x02000303U
 #define AST2500_A0_SILICON_REV   0x04000303U
+#define AST2500_A1_SILICON_REV   0x04010303U
 
 extern bool is_supported_silicon_rev(uint32_t silicon_rev);
 
@@ -145,4 +146,59 @@ extern bool is_supported_silicon_rev(uint32_t silicon_rev);
         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
         SCU_HW_STRAP_BOOT_MODE(SPI_BOOT))
 
+/*
+ * Hardware strapping register definition (for Aspeed AST2500 SOC and
+ * higher)
+ */
+#define SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE  (0x1 << 31)
+#define SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE     (0x1 << 30)
+#define SCU_AST2500_HW_STRAP_UART_DEBUG            (0x1 << 29)
+#define     UART_DEBUG_UART1                           0
+#define     UART_DEBUG_UART5                           1
+#define SCU_AST2500_HW_STRAP_RESERVED28            (0x1 << 28)
+
+#define SCU_AST2500_HW_STRAP_FAST_RESET_DBG        (0x1 << 27)
+#define SCU_AST2500_HW_STRAP_ESPI_FLASH_ENABLE     (0x1 << 26)
+#define SCU_AST2500_HW_STRAP_ESPI_ENABLE           (0x1 << 25)
+#define SCU_AST2500_HW_STRAP_DDR4_ENABLE           (0x1 << 24)
+
+#define SCU_AST2500_HW_STRAP_ACPI_ENABLE           (0x1 << 19)
+#define SCU_AST2500_HW_STRAP_USBCKI_FREQ           (0x1 << 18)
+#define     USBCKI_FREQ_24MHZ                          0
+#define     USBCKI_FREQ_28MHZ                          1
+
+#define SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(x)  (x << 9)
+#define SCU_AST2500_HW_STRAP_GET_AXI_AHB_RATIO(x)  ((x >> 9) & 7)
+#define SCU_AST2500_HW_STRAP_CPU_AXI_RATIO_MASK    (0x7 << 9)
+#define     AXI_AHB_RATIO_UNDEFINED                    0
+#define     AXI_AHB_RATIO_2_1                          1
+#define     AXI_AHB_RATIO_3_1                          2
+#define     AXI_AHB_RATIO_4_1                          3
+#define     AXI_AHB_RATIO_5_1                          4
+#define     AXI_AHB_RATIO_6_1                          5
+#define     AXI_AHB_RATIO_7_1                          6
+#define     AXI_AHB_RATIO_8_1                          7
+
+#define SCU_AST2500_HW_STRAP_RESERVED1             (0x1 << 1)
+#define SCU_AST2500_HW_STRAP_DIS_BOOT              (0x1 << 0)
+
+#define AST2500_HW_STRAP1_DEFAULTS (                                    \
+        SCU_AST2500_HW_STRAP_RESERVED28 |                               \
+        SCU_HW_STRAP_2ND_BOOT_WDT |                                     \
+        SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
+        SCU_HW_STRAP_LPC_RESET_PIN |                                    \
+        SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) |     \
+        SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
+        SCU_AST2500_HW_STRAP_RESERVED1)
+
+#define AST2500_HW_STRAP1 ((                                            \
+        AST2500_HW_STRAP1_DEFAULTS |                                    \
+        SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
+        SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
+        SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
+        SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
+        SCU_HW_STRAP_MAC1_RGMII |                                       \
+        SCU_HW_STRAP_MAC0_RGMII) &                                      \
+        ~SCU_HW_STRAP_2ND_BOOT_WDT)
+
 #endif /* ASPEED_SCU_H */
-- 
2.1.4

[Qemu-devel] [PATCH v2 8/9] arm: add support for an ast2500 evaluation board

[Cédric Le Goater]

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---

 Changes since v1:

 - changed AST2500_EDK to AST2500_EVB
 - fixed white space issues
 - added AST2500_HW_STRAP1 

 hw/arm/aspeed.c          | 31 ++++++++++++++++++++++++++++++-
 include/hw/arm/ast2400.h |  5 +++++
 2 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index b5d34a3a0367..c8812cc358bb 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -37,12 +37,15 @@ typedef struct AspeedBoardConfig {
 } AspeedBoardConfig;
 
 enum {
-    PALMETTO_BMC
+    PALMETTO_BMC,
+    AST2500_EVB
 };
 
 static const AspeedBoardConfig aspeed_boards[] = {
     [PALMETTO_BMC] = { AST2400_HW_STRAP1, AST2400_A0_SILICON_REV,
                        AST2400_SDRAM_BASE },
+    [AST2500_EVB]  = { AST2500_HW_STRAP1, AST2500_A1_SILICON_REV,
+                       AST2500_SDRAM_BASE },
 };
 
 static void aspeed_init_flashes(AspeedSMCState *s, const char *flashtype,
@@ -130,9 +133,35 @@ static const TypeInfo palmetto_bmc_type = {
     .class_init = palmetto_bmc_class_init,
 };
 
+static void ast2500_evb_init(MachineState *machine)
+{
+    machine->cpu_model = "arm1176";
+    aspeed_init(machine, &aspeed_boards[AST2500_EVB]);
+}
+
+static void ast2500_evb_class_init(ObjectClass *oc, void *data)
+{
+    MachineClass *mc = MACHINE_CLASS(oc);
+
+    mc->desc = "Aspeed AST2500 EVB (ARM1176)";
+    mc->init = ast2500_evb_init;
+    mc->max_cpus = 1;
+    mc->no_sdcard = 1;
+    mc->no_floppy = 1;
+    mc->no_cdrom = 1;
+    mc->no_parallel = 1;
+}
+
+static const TypeInfo ast2500_evb_type = {
+    .name = MACHINE_TYPE_NAME("ast2500-evb"),
+    .parent = TYPE_MACHINE,
+    .class_init = ast2500_evb_class_init,
+};
+
 static void aspeed_machine_init(void)
 {
     type_register_static(&palmetto_bmc_type);
+    type_register_static(&ast2500_evb_type);
 }
 
 type_init(aspeed_machine_init)
diff --git a/include/hw/arm/ast2400.h b/include/hw/arm/ast2400.h
index e68807d475b7..2e6864f88790 100644
--- a/include/hw/arm/ast2400.h
+++ b/include/hw/arm/ast2400.h
@@ -41,4 +41,9 @@ typedef struct AST2400State {
 
 #define AST2400_SDRAM_BASE       0x40000000
 
+/*
+ * for Aspeed AST2500 SOC and higher
+ */
+#define AST2500_SDRAM_BASE       0x80000000
+
 #endif /* AST2400_H */
-- 
2.1.4

[Qemu-devel] [PATCH v2 9/9] palmetto-bmc: remove extra no_sdcard assignement

[Cédric Le Goater]

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index c8812cc358bb..e658611df37a 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -123,7 +123,6 @@ static void palmetto_bmc_class_init(ObjectClass *oc, void *data)
     mc->no_sdcard = 1;
     mc->no_floppy = 1;
     mc->no_cdrom = 1;
-    mc->no_sdcard = 1;
     mc->no_parallel = 1;
 }
 
-- 
2.1.4