From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net
Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com,
bharata@linux.vnet.ibm.com, aneesh.kumar@linux.vnet.ibm.com,
benh@kernel.crashing.org,
Sandipan Das <sandipandas1990@gmail.com>
Subject: [Qemu-devel] [PATCH v2 3/8] target-ppc: add dtstsfi[q] instructions
Date: Thu, 28 Jul 2016 23:44:13 +0530 [thread overview]
Message-ID: <1469729658-4832-4-git-send-email-nikunj@linux.vnet.ibm.com> (raw)
In-Reply-To: <1469729658-4832-1-git-send-email-nikunj@linux.vnet.ibm.com>
From: Sandipan Das <sandipandas1990@gmail.com>
DFP Test Significance Immediate [Quad]
Signed-off-by: Sandipan Das <sandipandas1990@gmail.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/dfp_helper.c | 35 +++++++++++++++++++++++++++++++++++
target-ppc/helper.h | 2 ++
target-ppc/translate/dfp-impl.c | 20 ++++++++++++++++++++
target-ppc/translate/dfp-ops.c | 14 ++++++++++++++
4 files changed, 71 insertions(+)
diff --git a/target-ppc/dfp_helper.c b/target-ppc/dfp_helper.c
index db0ede6..9164fe7 100644
--- a/target-ppc/dfp_helper.c
+++ b/target-ppc/dfp_helper.c
@@ -647,6 +647,41 @@ uint32_t helper_##op(CPUPPCState *env, uint64_t *a, uint64_t *b) \
DFP_HELPER_TSTSF(dtstsf, 64)
DFP_HELPER_TSTSF(dtstsfq, 128)
+#define DFP_HELPER_TSTSFI(op, size) \
+uint32_t helper_##op(CPUPPCState *env, uint32_t a, uint64_t *b) \
+{ \
+ struct PPC_DFP dfp; \
+ unsigned uim; \
+ \
+ dfp_prepare_decimal##size(&dfp, 0, b, env); \
+ \
+ uim = a & 0x3F; \
+ \
+ if (unlikely(decNumberIsSpecial(&dfp.b))) { \
+ dfp.crbf = 1; \
+ } else if (uim == 0) { \
+ dfp.crbf = 4; \
+ } else if (unlikely(decNumberIsZero(&dfp.b))) { \
+ /* Zero has no sig digits */ \
+ dfp.crbf = 4; \
+ } else { \
+ unsigned nsd = dfp.b.digits; \
+ if (uim < nsd) { \
+ dfp.crbf = 8; \
+ } else if (uim > nsd) { \
+ dfp.crbf = 4; \
+ } else { \
+ dfp.crbf = 2; \
+ } \
+ } \
+ \
+ dfp_set_FPCC_from_CRBF(&dfp); \
+ return dfp.crbf; \
+}
+
+DFP_HELPER_TSTSFI(dtstsfi, 64)
+DFP_HELPER_TSTSFI(dtstsfiq, 128)
+
static void QUA_PPs(struct PPC_DFP *dfp)
{
dfp_set_FPRF_from_FRT(dfp);
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 3b6e6e6..27f2638 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -647,6 +647,8 @@ DEF_HELPER_3(dtstex, i32, env, fprp, fprp)
DEF_HELPER_3(dtstexq, i32, env, fprp, fprp)
DEF_HELPER_3(dtstsf, i32, env, fprp, fprp)
DEF_HELPER_3(dtstsfq, i32, env, fprp, fprp)
+DEF_HELPER_3(dtstsfi, i32, env, i32, fprp)
+DEF_HELPER_3(dtstsfiq, i32, env, i32, fprp)
DEF_HELPER_5(dquai, void, env, fprp, fprp, i32, i32)
DEF_HELPER_5(dquaiq, void, env, fprp, fprp, i32, i32)
DEF_HELPER_5(dqua, void, env, fprp, fprp, fprp, i32)
diff --git a/target-ppc/translate/dfp-impl.c b/target-ppc/translate/dfp-impl.c
index bf59951..178d304 100644
--- a/target-ppc/translate/dfp-impl.c
+++ b/target-ppc/translate/dfp-impl.c
@@ -45,6 +45,24 @@ static void gen_##name(DisasContext *ctx) \
tcg_temp_free_ptr(rb); \
}
+#define GEN_DFP_BF_I_B(name) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_i32 uim; \
+ TCGv_ptr rb; \
+ if (unlikely(!ctx->fpu_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_FPU); \
+ return; \
+ } \
+ gen_update_nip(ctx, ctx->nip - 4); \
+ uim = tcg_const_i32(UIMM5(ctx->opcode)); \
+ rb = gen_fprp_ptr(rB(ctx->opcode)); \
+ gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
+ cpu_env, uim, rb); \
+ tcg_temp_free_i32(uim); \
+ tcg_temp_free_ptr(rb); \
+}
+
#define GEN_DFP_BF_A_DCM(name) \
static void gen_##name(DisasContext *ctx) \
{ \
@@ -172,6 +190,8 @@ GEN_DFP_BF_A_B(dtstex)
GEN_DFP_BF_A_B(dtstexq)
GEN_DFP_BF_A_B(dtstsf)
GEN_DFP_BF_A_B(dtstsfq)
+GEN_DFP_BF_I_B(dtstsfi)
+GEN_DFP_BF_I_B(dtstsfiq)
GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
diff --git a/target-ppc/translate/dfp-ops.c b/target-ppc/translate/dfp-ops.c
index 7f27d0f..6ef38e5 100644
--- a/target-ppc/translate/dfp-ops.c
+++ b/target-ppc/translate/dfp-ops.c
@@ -1,6 +1,9 @@
#define _GEN_DFP_LONG(name, op1, op2, mask) \
GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
+#define _GEN_DFP_LONG_300(name, op1, op2, mask) \
+GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_ISA300)
+
#define _GEN_DFP_LONGx2(name, op1, op2, mask) \
GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
@@ -14,6 +17,9 @@ GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
#define _GEN_DFP_QUAD(name, op1, op2, mask) \
GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
+#define _GEN_DFP_QUAD_300(name, op1, op2, mask) \
+GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_ISA300)
+
#define _GEN_DFP_QUADx2(name, op1, op2, mask) \
GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
@@ -48,12 +54,18 @@ _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
#define GEN_DFP_BF_A_B(name, op1, op2) \
_GEN_DFP_LONG(name, op1, op2, 0x00000001)
+#define GEN_DFP_BF_A_B_300(name, op1, op2) \
+_GEN_DFP_LONG_300(name, op1, op2, 0x00400001)
+
#define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
_GEN_DFP_QUAD(name, op1, op2, 0x00610801)
#define GEN_DFP_BF_A_Bp(name, op1, op2) \
_GEN_DFP_QUAD(name, op1, op2, 0x00600801)
+#define GEN_DFP_BF_A_Bp_300(name, op1, op2) \
+_GEN_DFP_QUAD_300(name, op1, op2, 0x00400001)
+
#define GEN_DFP_BF_A_DCM(name, op1, op2) \
_GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
@@ -119,6 +131,8 @@ GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
+GEN_DFP_BF_A_B_300(dtstsfi, 0x03, 0x15),
+GEN_DFP_BF_A_Bp_300(dtstsfiq, 0x03, 0x15),
GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
--
2.7.4
next prev parent reply other threads:[~2016-07-28 18:14 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-28 18:14 [Qemu-devel] [PATCH v2 0/8] POWER9 TCG enablements - part2 Nikunj A Dadhania
2016-07-28 18:14 ` [Qemu-devel] [PATCH v2 1/8] target-ppc: implement branch-less divw[o][.] Nikunj A Dadhania
2016-07-28 18:14 ` [Qemu-devel] [PATCH v2 2/8] target-ppc: implement branch-less divd[o][.] Nikunj A Dadhania
2016-07-28 18:14 ` Nikunj A Dadhania [this message]
2016-07-28 18:14 ` [Qemu-devel] [PATCH v2 4/8] target-ppc: add vabsdu[b, h, w] instructions Nikunj A Dadhania
2016-07-29 1:01 ` Richard Henderson
2016-07-28 18:14 ` [Qemu-devel] [PATCH v2 5/8] target-ppc: add vcmpnez[b, h, w][.] instructions Nikunj A Dadhania
2016-07-29 1:02 ` Richard Henderson
2016-07-28 18:14 ` [Qemu-devel] [PATCH v2 6/8] target-ppc: add vslv instruction Nikunj A Dadhania
2016-07-28 18:14 ` [Qemu-devel] [PATCH v2 7/8] target-ppc: add vsrv instruction Nikunj A Dadhania
2016-07-28 18:14 ` [Qemu-devel] [PATCH v2 8/8] target-ppc: add extswsli[.] instruction Nikunj A Dadhania
2016-07-29 4:35 ` [Qemu-devel] [PATCH v2 0/8] POWER9 TCG enablements - part2 David Gibson
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