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From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net
Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com,
	bharata@linux.vnet.ibm.com, aneesh.kumar@linux.vnet.ibm.com,
	benh@kernel.crashing.org,
	Vivek Andrew Sha <vivekandrewsha@gmail.com>
Subject: [Qemu-devel] [PATCH v2 6/8] target-ppc: add vslv instruction
Date: Thu, 28 Jul 2016 23:44:16 +0530	[thread overview]
Message-ID: <1469729658-4832-7-git-send-email-nikunj@linux.vnet.ibm.com> (raw)
In-Reply-To: <1469729658-4832-1-git-send-email-nikunj@linux.vnet.ibm.com>

From: Vivek Andrew Sha <vivekandrewsha@gmail.com>

vslv: Vector Shift Left Variable

Signed-off-by: Vivek Andrew Sha <vivekandrewsha@gmail.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
 target-ppc/helper.h             |  1 +
 target-ppc/int_helper.c         | 14 ++++++++++++++
 target-ppc/translate/vmx-impl.c |  1 +
 target-ppc/translate/vmx-ops.c  |  4 ++++
 4 files changed, 20 insertions(+)

diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index e6ce3ab..d4c060b 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -211,6 +211,7 @@ DEF_HELPER_3(vslw, void, avr, avr, avr)
 DEF_HELPER_3(vsld, void, avr, avr, avr)
 DEF_HELPER_3(vslo, void, avr, avr, avr)
 DEF_HELPER_3(vsro, void, avr, avr, avr)
+DEF_HELPER_3(vslv, void, avr, avr, avr)
 DEF_HELPER_3(vaddcuw, void, avr, avr, avr)
 DEF_HELPER_3(vsubcuw, void, avr, avr, avr)
 DEF_HELPER_2(lvsl, void, avr, tl)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 9b4de69..12fe144 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -1696,6 +1696,20 @@ VSL(w, u32, 0x1F)
 VSL(d, u64, 0x3F)
 #undef VSL
 
+void helper_vslv(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+    int i;
+    unsigned int shift, bytes, size;
+
+    size = ARRAY_SIZE(r->u8);
+    for (i = 0; i < size; i++) {
+        shift = b->u8[i] & 0x7;             /* extract shift value */
+        bytes = (a->u8[i] << 8) +             /* extract adjacent bytes */
+            (((i + 1) < size) ? a->u8[i + 1] : 0);
+        r->u8[i] = (bytes << shift) >> 8;   /* shift and store result */
+    }
+}
+
 void helper_vsldoi(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t shift)
 {
     int sh = shift & 0xf;
diff --git a/target-ppc/translate/vmx-impl.c b/target-ppc/translate/vmx-impl.c
index da11632..5844a7e 100644
--- a/target-ppc/translate/vmx-impl.c
+++ b/target-ppc/translate/vmx-impl.c
@@ -367,6 +367,7 @@ GEN_VXFORM(vsrab, 2, 12);
 GEN_VXFORM(vsrah, 2, 13);
 GEN_VXFORM(vsraw, 2, 14);
 GEN_VXFORM(vsrad, 2, 15);
+GEN_VXFORM(vslv, 2, 29);
 GEN_VXFORM(vslo, 6, 16);
 GEN_VXFORM(vsro, 6, 17);
 GEN_VXFORM(vaddcuw, 0, 6);
diff --git a/target-ppc/translate/vmx-ops.c b/target-ppc/translate/vmx-ops.c
index 137f00b..ffc4443 100644
--- a/target-ppc/translate/vmx-ops.c
+++ b/target-ppc/translate/vmx-ops.c
@@ -38,6 +38,9 @@ GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
 #define GEN_VXFORM_207(name, opc2, opc3) \
 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
 
+#define GEN_VXFORM_300(name, opc2, opc3)                                \
+GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA300)
+
 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
 
@@ -107,6 +110,7 @@ GEN_VXFORM(vsrab, 2, 12),
 GEN_VXFORM(vsrah, 2, 13),
 GEN_VXFORM(vsraw, 2, 14),
 GEN_VXFORM_207(vsrad, 2, 15),
+GEN_VXFORM_300(vslv, 2, 29),
 GEN_VXFORM(vslo, 6, 16),
 GEN_VXFORM(vsro, 6, 17),
 GEN_VXFORM(vaddcuw, 0, 6),
-- 
2.7.4

  parent reply	other threads:[~2016-07-28 18:14 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-07-28 18:14 [Qemu-devel] [PATCH v2 0/8] POWER9 TCG enablements - part2 Nikunj A Dadhania
2016-07-28 18:14 ` [Qemu-devel] [PATCH v2 1/8] target-ppc: implement branch-less divw[o][.] Nikunj A Dadhania
2016-07-28 18:14 ` [Qemu-devel] [PATCH v2 2/8] target-ppc: implement branch-less divd[o][.] Nikunj A Dadhania
2016-07-28 18:14 ` [Qemu-devel] [PATCH v2 3/8] target-ppc: add dtstsfi[q] instructions Nikunj A Dadhania
2016-07-28 18:14 ` [Qemu-devel] [PATCH v2 4/8] target-ppc: add vabsdu[b, h, w] instructions Nikunj A Dadhania
2016-07-29  1:01   ` Richard Henderson
2016-07-28 18:14 ` [Qemu-devel] [PATCH v2 5/8] target-ppc: add vcmpnez[b, h, w][.] instructions Nikunj A Dadhania
2016-07-29  1:02   ` Richard Henderson
2016-07-28 18:14 ` Nikunj A Dadhania [this message]
2016-07-28 18:14 ` [Qemu-devel] [PATCH v2 7/8] target-ppc: add vsrv instruction Nikunj A Dadhania
2016-07-28 18:14 ` [Qemu-devel] [PATCH v2 8/8] target-ppc: add extswsli[.] instruction Nikunj A Dadhania
2016-07-29  4:35 ` [Qemu-devel] [PATCH v2 0/8] POWER9 TCG enablements - part2 David Gibson

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