From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39403) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bSpph-0007Fd-BM for qemu-devel@nongnu.org; Thu, 28 Jul 2016 14:14:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bSppe-00019L-3y for qemu-devel@nongnu.org; Thu, 28 Jul 2016 14:14:57 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:61242 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bSppd-00019H-UP for qemu-devel@nongnu.org; Thu, 28 Jul 2016 14:14:54 -0400 Received: from pps.filterd (m0098413.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id u6SIC7SO083649 for ; Thu, 28 Jul 2016 14:14:53 -0400 Received: from e28smtp05.in.ibm.com (e28smtp05.in.ibm.com [125.16.236.5]) by mx0b-001b2d01.pphosted.com with ESMTP id 24e4egk31y-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 28 Jul 2016 14:14:53 -0400 Received: from localhost by e28smtp05.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 28 Jul 2016 23:44:50 +0530 From: Nikunj A Dadhania Date: Thu, 28 Jul 2016 23:44:16 +0530 In-Reply-To: <1469729658-4832-1-git-send-email-nikunj@linux.vnet.ibm.com> References: <1469729658-4832-1-git-send-email-nikunj@linux.vnet.ibm.com> Message-Id: <1469729658-4832-7-git-send-email-nikunj@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH v2 6/8] target-ppc: add vslv instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com, bharata@linux.vnet.ibm.com, aneesh.kumar@linux.vnet.ibm.com, benh@kernel.crashing.org, Vivek Andrew Sha From: Vivek Andrew Sha vslv: Vector Shift Left Variable Signed-off-by: Vivek Andrew Sha Signed-off-by: Nikunj A Dadhania Reviewed-by: David Gibson Reviewed-by: Richard Henderson --- target-ppc/helper.h | 1 + target-ppc/int_helper.c | 14 ++++++++++++++ target-ppc/translate/vmx-impl.c | 1 + target-ppc/translate/vmx-ops.c | 4 ++++ 4 files changed, 20 insertions(+) diff --git a/target-ppc/helper.h b/target-ppc/helper.h index e6ce3ab..d4c060b 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -211,6 +211,7 @@ DEF_HELPER_3(vslw, void, avr, avr, avr) DEF_HELPER_3(vsld, void, avr, avr, avr) DEF_HELPER_3(vslo, void, avr, avr, avr) DEF_HELPER_3(vsro, void, avr, avr, avr) +DEF_HELPER_3(vslv, void, avr, avr, avr) DEF_HELPER_3(vaddcuw, void, avr, avr, avr) DEF_HELPER_3(vsubcuw, void, avr, avr, avr) DEF_HELPER_2(lvsl, void, avr, tl) diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c index 9b4de69..12fe144 100644 --- a/target-ppc/int_helper.c +++ b/target-ppc/int_helper.c @@ -1696,6 +1696,20 @@ VSL(w, u32, 0x1F) VSL(d, u64, 0x3F) #undef VSL +void helper_vslv(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) +{ + int i; + unsigned int shift, bytes, size; + + size = ARRAY_SIZE(r->u8); + for (i = 0; i < size; i++) { + shift = b->u8[i] & 0x7; /* extract shift value */ + bytes = (a->u8[i] << 8) + /* extract adjacent bytes */ + (((i + 1) < size) ? a->u8[i + 1] : 0); + r->u8[i] = (bytes << shift) >> 8; /* shift and store result */ + } +} + void helper_vsldoi(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t shift) { int sh = shift & 0xf; diff --git a/target-ppc/translate/vmx-impl.c b/target-ppc/translate/vmx-impl.c index da11632..5844a7e 100644 --- a/target-ppc/translate/vmx-impl.c +++ b/target-ppc/translate/vmx-impl.c @@ -367,6 +367,7 @@ GEN_VXFORM(vsrab, 2, 12); GEN_VXFORM(vsrah, 2, 13); GEN_VXFORM(vsraw, 2, 14); GEN_VXFORM(vsrad, 2, 15); +GEN_VXFORM(vslv, 2, 29); GEN_VXFORM(vslo, 6, 16); GEN_VXFORM(vsro, 6, 17); GEN_VXFORM(vaddcuw, 0, 6); diff --git a/target-ppc/translate/vmx-ops.c b/target-ppc/translate/vmx-ops.c index 137f00b..ffc4443 100644 --- a/target-ppc/translate/vmx-ops.c +++ b/target-ppc/translate/vmx-ops.c @@ -38,6 +38,9 @@ GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) #define GEN_VXFORM_207(name, opc2, opc3) \ GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207) +#define GEN_VXFORM_300(name, opc2, opc3) \ +GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA300) + #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \ GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1) @@ -107,6 +110,7 @@ GEN_VXFORM(vsrab, 2, 12), GEN_VXFORM(vsrah, 2, 13), GEN_VXFORM(vsraw, 2, 14), GEN_VXFORM_207(vsrad, 2, 15), +GEN_VXFORM_300(vslv, 2, 29), GEN_VXFORM(vslo, 6, 16), GEN_VXFORM(vsro, 6, 17), GEN_VXFORM(vaddcuw, 0, 6), -- 2.7.4