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From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: Fri, 29 Jul 2016 12:13:01 +1000
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Subject: Re: [Qemu-devel] [PATCH 28/32] ppc: Avoid double translation for
 lvx/lvxl/stvx/stvxl
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To: Richard Henderson <rth@twiddle.net>, qemu-ppc@nongnu.org
Cc: qemu-devel@nongnu.org, david@gibson.dropbear.id.au

On Fri, 2016-07-29 at 06:19 +0530, Richard Henderson wrote:
> This, I'm not so keen on.
>=20
> (1) The helper, since it writes to registers controlled by tcg, must be=
=C2=A0
> described to clobber all registers.=C2=A0 Which will noticeably increas=
e memory=C2=A0
> traffic to ENV.=C2=A0 For instance, you won't be able to hold the guest=
 register=C2=A0
> holding the address in a host register across the call.

Ah I wasn't aware of this. How do you describe such a clobber ? Can I des=
cribe
specifically which one is clobbered ? I didn't think TCG kept track of th=
e vector
halves but I must admit I'm still a bit new with TCG in general.

I noticed other constructs doing that (passing a register number to an op=
code),
what do I do to ensure the right clobbers are there ?

> > (2) We're going to have to teach tcg about 16-byte data types soon an=
yway, for=C2=A0
> the proper emulation of 16-byte atomic operations.

Is anybody working on this already ? I thought about that approach as
it would definitely make things easier for that and a couple of other
cases such as lq/stq.

Cheers,
Ben.