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From: Leon Alrae <leon.alrae@imgtec.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 2/2] target-mips: fix EntryHi.EHINV being cleared on TLB exception
Date: Fri, 29 Jul 2016 10:11:12 +0100	[thread overview]
Message-ID: <1469783472-18639-3-git-send-email-leon.alrae@imgtec.com> (raw)
In-Reply-To: <1469783472-18639-1-git-send-email-leon.alrae@imgtec.com>

While implementing TLB invalidation feature we forgot to modify
part of code responsible for updating EntryHi during TLB exception.
Consequently EntryHi.EHINV is unexpectedly cleared on the exception.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 target-mips/helper.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target-mips/helper.c b/target-mips/helper.c
index 9fbca26..c864b15 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -396,6 +396,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
     env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
                        ((address >> 9) & 0x007ffff0);
     env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) |
+                       (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) |
                        (address & (TARGET_PAGE_MASK << 1));
 #if defined(TARGET_MIPS64)
     env->CP0_EntryHi &= env->SEGMask;
-- 
2.7.4

  parent reply	other threads:[~2016-07-29  9:11 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-07-29  9:11 [Qemu-devel] [PULL 0/2] target-mips queue Leon Alrae
2016-07-29  9:11 ` [Qemu-devel] [PULL 1/2] hw/mips_malta: Fix YAMON API print routine Leon Alrae
2016-07-29  9:11 ` Leon Alrae [this message]
2016-07-29 12:54 ` [Qemu-devel] [PULL 0/2] target-mips queue Peter Maydell

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