From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35869) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bUfXc-0006ao-N9 for qemu-devel@nongnu.org; Tue, 02 Aug 2016 15:39:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bUfXb-0003WZ-IE for qemu-devel@nongnu.org; Tue, 02 Aug 2016 15:39:52 -0400 Sender: Paolo Bonzini From: Paolo Bonzini Date: Tue, 2 Aug 2016 21:39:19 +0200 Message-Id: <1470166775-3671-10-git-send-email-pbonzini@redhat.com> In-Reply-To: <1470166775-3671-1-git-send-email-pbonzini@redhat.com> References: <1470166775-3671-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PULL 09/25] target-i386: fix typo in xsetbv implementation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Dave Hansen , qemu-stable@nongnu.org, Eduardo Habkost From: Dave Hansen QEMU 2.6 added support for the XSAVE family of instructions, which includes the XSETBV instruction which allows setting the XCR0 register. But, when booting Linux kernels with XSAVE support enabled, I was getting very early crashes where the instruction pointer was set to 0x3. I tracked it down to a jump instruction generated by this: gen_jmp_im(s->pc - pc_start); where s->pc is pointing to the instruction after XSETBV and pc_start is pointing _at_ XSETBV. Subtract the two and you get 0x3. Whoops. The fix is to replace this typo with the pattern found everywhere else in the file when folks want to end the translation buffer. Richard Henderson confirmed that this is a bug and that this is the correct fix. Signed-off-by: Dave Hansen Cc: qemu-stable@nongnu.org Cc: Eduardo Habkost Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- target-i386/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index e81fce7..fa2ac48 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -7176,7 +7176,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[R_ECX]); gen_helper_xsetbv(cpu_env, cpu_tmp2_i32, cpu_tmp1_i64); /* End TB because translation flags may change. */ - gen_jmp_im(s->pc - pc_start); + gen_jmp_im(s->pc - s->cs_base); gen_eob(s); break; -- 2.7.4