Re: [Qemu-devel] [PATCH v3 03/10] aspeed-soc: provide a framework to add new SoCs

[Andrew Jeffery <andrew@aj.id.au>]

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On Tue, 2016-08-02 at 19:15 +0200, Cédric Le Goater wrote:
> Let's define an object class for each Aspeed SoC we support. A
> AspeedSoCInfo struct gathers the SoC specifications which can later
> be
> used by an instance of the class or by a board using the SoC.
> 
> Signed-off-by: Cédric Le Goater <clg@kaod.org>

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>

> ---
>  hw/arm/aspeed_soc.c         | 27 ++++++++++++++++++++++++---
>  hw/arm/palmetto-bmc.c       | 12 ++++++++----
>  include/hw/arm/aspeed_soc.h | 17 ++++++++++++++++-
>  3 files changed, 48 insertions(+), 8 deletions(-)
> 
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
> index 1bec478fef68..ec6ec3546908 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_soc.c
> @@ -37,6 +37,13 @@
>  static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
>  static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
>  
> +#define AST2400_SDRAM_BASE       0x40000000
> +
> +static const AspeedSoCInfo aspeed_socs[] = {
> +    { "ast2400-a0", "arm926", AST2400_A0_SILICON_REV,
> AST2400_SDRAM_BASE },
> +    { "ast2400",    "arm926", AST2400_A0_SILICON_REV,
> AST2400_SDRAM_BASE },
> +};
> +
>  /*
>   * IO handlers: simply catch any reads/writes to IO addresses that
> aren't
>   * handled by a device mapping.
> @@ -65,8 +72,9 @@ static const MemoryRegionOps aspeed_soc_io_ops = {
>  static void aspeed_soc_init(Object *obj)
>  {
>      AspeedSoCState *s = ASPEED_SOC(obj);
> +    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
>  
> -    s->cpu = cpu_arm_init("arm926");
> +    s->cpu = cpu_arm_init(sc->info->cpu_model);
>  
>      object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);
>      object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);
> @@ -84,7 +92,7 @@ static void aspeed_soc_init(Object *obj)
>      object_property_add_child(obj, "scu", OBJECT(&s->scu), NULL);
>      qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());
>      qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
> -                         AST2400_A0_SILICON_REV);
> +                         sc->info->silicon_rev);
>      object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
>                                "hw-strap1", &error_abort);
>      object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
> @@ -102,7 +110,7 @@ static void aspeed_soc_init(Object *obj)
>      object_property_add_child(obj, "sdmc", OBJECT(&s->sdmc), NULL);
>      qdev_set_parent_bus(DEVICE(&s->sdmc), sysbus_get_default());
>      qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev",
> -                         AST2400_A0_SILICON_REV);
> +                         sc->info->silicon_rev);
>  }
>  
>  static void aspeed_soc_realize(DeviceState *dev, Error **errp)
> @@ -202,7 +210,9 @@ static void aspeed_soc_realize(DeviceState *dev,
> Error **errp)
>  static void aspeed_soc_class_init(ObjectClass *oc, void *data)
>  {
>      DeviceClass *dc = DEVICE_CLASS(oc);
> +    AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
>  
> +    sc->info = (AspeedSoCInfo *) data;
>      dc->realize = aspeed_soc_realize;
>  
>      /*
> @@ -222,7 +232,18 @@ static const TypeInfo aspeed_soc_type_info = {
>  
>  static void aspeed_soc_register_types(void)
>  {
> +    int i;
> +
>      type_register_static(&aspeed_soc_type_info);
> +    for (i = 0; i < ARRAY_SIZE(aspeed_socs); ++i) {
> +        TypeInfo ti = {
> +            .name       = aspeed_socs[i].name,
> +            .parent     = TYPE_ASPEED_SOC,
> +            .class_init = aspeed_soc_class_init,
> +            .class_data = (void *) &aspeed_socs[i],
> +        };
> +        type_register(&ti);
> +    }
>  }
>  
>  type_init(aspeed_soc_register_types)
> diff --git a/hw/arm/palmetto-bmc.c b/hw/arm/palmetto-bmc.c
> index 4d11905cfb18..531c266d9449 100644
> --- a/hw/arm/palmetto-bmc.c
> +++ b/hw/arm/palmetto-bmc.c
> @@ -22,8 +22,6 @@
>  #include "sysemu/blockdev.h"
>  
>  static struct arm_boot_info palmetto_bmc_binfo = {
> -    .loader_start = AST2400_SDRAM_BASE,
> -    .board_id = 0,
>      .nb_cpus = 1,
>  };
>  
> @@ -61,14 +59,17 @@ static void
> palmetto_bmc_init_flashes(AspeedSMCState *s, const char *flashtype,
>  static void palmetto_bmc_init(MachineState *machine)
>  {
>      PalmettoBMCState *bmc;
> +    AspeedSoCClass *sc;
>  
>      bmc = g_new0(PalmettoBMCState, 1);
> -    object_initialize(&bmc->soc, (sizeof(bmc->soc)),
> TYPE_ASPEED_SOC);
> +    object_initialize(&bmc->soc, (sizeof(bmc->soc)), "ast2400-a0");
>      object_property_add_child(OBJECT(machine), "soc", OBJECT(&bmc-
> >soc),
>                                &error_abort);
>  
> +    sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
> +
>      memory_region_allocate_system_memory(&bmc->ram, NULL, "ram",
> ram_size);
> -    memory_region_add_subregion(get_system_memory(),
> AST2400_SDRAM_BASE,
> +    memory_region_add_subregion(get_system_memory(), sc->info-
> >sdram_base,
>                                  &bmc->ram);
>      object_property_add_const_link(OBJECT(&bmc->soc), "ram",
> OBJECT(&bmc->ram),
>                                     &error_abort);
> @@ -84,6 +85,9 @@ static void palmetto_bmc_init(MachineState
> *machine)
>      palmetto_bmc_binfo.initrd_filename = machine->initrd_filename;
>      palmetto_bmc_binfo.kernel_cmdline = machine->kernel_cmdline;
>      palmetto_bmc_binfo.ram_size = ram_size;
> +    palmetto_bmc_binfo.board_id = sc->info->silicon_rev;
> +    palmetto_bmc_binfo.loader_start = sc->info->sdram_base;
> +
>      arm_load_kernel(ARM_CPU(first_cpu), &palmetto_bmc_binfo);
>  }
>  
> diff --git a/include/hw/arm/aspeed_soc.h
> b/include/hw/arm/aspeed_soc.h
> index bf63ae90cabe..0146a2a54a0e 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -39,6 +39,21 @@ typedef struct AspeedSoCState {
>  #define TYPE_ASPEED_SOC "aspeed-soc"
>  #define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj),
> TYPE_ASPEED_SOC)
>  
> -#define AST2400_SDRAM_BASE       0x40000000
> +typedef struct AspeedSoCInfo {
> +    const char *name;
> +    const char *cpu_model;
> +    uint32_t silicon_rev;
> +    hwaddr sdram_base;
> +} AspeedSoCInfo;
> +
> +typedef struct AspeedSoCClass {
> +    DeviceState parent_class;
> +    AspeedSoCInfo *info;
> +} AspeedSoCClass;
> +
> +#define
> ASPEED_SOC_CLASS(klass)                                         \
> +    OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC)
> +#define ASPEED_SOC_GET_CLASS(obj)                               \
> +    OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC)
>  
>  #endif /* ASPEED_SOC_H */

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