From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43829) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bWS0g-0004GK-1P for qemu-devel@nongnu.org; Sun, 07 Aug 2016 13:37:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bWS0b-0005Ck-RM for qemu-devel@nongnu.org; Sun, 07 Aug 2016 13:37:13 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:39501 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bWS0b-0005Ca-LN for qemu-devel@nongnu.org; Sun, 07 Aug 2016 13:37:09 -0400 Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id u77HYaSo101631 for ; Sun, 7 Aug 2016 13:37:09 -0400 Received: from e23smtp02.au.ibm.com (e23smtp02.au.ibm.com [202.81.31.144]) by mx0a-001b2d01.pphosted.com with ESMTP id 24nbvv4dps-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Sun, 07 Aug 2016 13:37:08 -0400 Received: from localhost by e23smtp02.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Mon, 8 Aug 2016 03:37:06 +1000 From: Nikunj A Dadhania Date: Sun, 7 Aug 2016 23:06:50 +0530 In-Reply-To: <1470591415-3268-1-git-send-email-nikunj@linux.vnet.ibm.com> References: <1470591415-3268-1-git-send-email-nikunj@linux.vnet.ibm.com> Message-Id: <1470591415-3268-2-git-send-email-nikunj@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH 1/6] target-ppc: add xxspltib instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com, benh@kernel.crashing.org xxspltib: VSX Vector Splat Immediate Byte Copy the immediate byte in each byte of target VSR Signed-off-by: Nikunj A Dadhania --- target-ppc/translate.c | 2 ++ target-ppc/translate/vsx-impl.inc.c | 20 ++++++++++++++++++++ target-ppc/translate/vsx-ops.inc.c | 5 +++++ 3 files changed, 27 insertions(+) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 0a5a3e2..2a87d1a 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -589,6 +589,8 @@ EXTRACT_HELPER(DM, 8, 2); EXTRACT_HELPER(UIM, 16, 2); EXTRACT_HELPER(SHW, 8, 2); EXTRACT_HELPER(SP, 19, 2); +EXTRACT_HELPER(IMM8, 11, 8); + /*****************************************************************************/ /* PowerPC instructions table */ diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c index 9f77b06..6e789cb 100644 --- a/target-ppc/translate/vsx-impl.inc.c +++ b/target-ppc/translate/vsx-impl.inc.c @@ -647,6 +647,26 @@ static void gen_xxspltw(DisasContext *ctx) tcg_temp_free_i64(b2); } +#define pattern(x) (((x) & 0xff) * (~(target_ulong)0 / 0xff)) + +static void gen_xxspltib(DisasContext *ctx) +{ + unsigned char uim8 = IMM8(ctx->opcode); + if (xS(ctx->opcode) < 32) { + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + } else { + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + } + tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), pattern(uim8)); + tcg_gen_movi_i64(cpu_vsrl(xT(ctx->opcode)), pattern(uim8)); +} + static void gen_xxsldwi(DisasContext *ctx) { TCGv_i64 xth, xtl; diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c index 8b9da65..62a6251 100644 --- a/target-ppc/translate/vsx-ops.inc.c +++ b/target-ppc/translate/vsx-ops.inc.c @@ -20,6 +20,10 @@ GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207), GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207), #endif +#define GEN_XX1FORM(name, opc2, opc3, fl2) \ +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \ +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2) + #define GEN_XX2FORM(name, opc2, opc3, fl2) \ GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \ GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2) @@ -222,6 +226,7 @@ VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207), GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX), GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX), GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX), +GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300), GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00), #define GEN_XXSEL_ROW(opc3) \ -- 2.7.4