From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37362) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bXYks-0007Fs-Q1 for qemu-devel@nongnu.org; Wed, 10 Aug 2016 15:01:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bXYkp-00088D-WD for qemu-devel@nongnu.org; Wed, 10 Aug 2016 15:01:30 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:6384 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bXYkp-000886-RV for qemu-devel@nongnu.org; Wed, 10 Aug 2016 15:01:27 -0400 Received: from pps.filterd (m0098414.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id u7AIxMFM082092 for ; Wed, 10 Aug 2016 15:01:27 -0400 Received: from e28smtp06.in.ibm.com (e28smtp06.in.ibm.com [125.16.236.6]) by mx0b-001b2d01.pphosted.com with ESMTP id 24qm9sb7h6-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 10 Aug 2016 15:01:27 -0400 Received: from localhost by e28smtp06.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 11 Aug 2016 00:31:22 +0530 From: Nikunj A Dadhania Date: Thu, 11 Aug 2016 00:30:58 +0530 In-Reply-To: <1470855666-31696-1-git-send-email-nikunj@linux.vnet.ibm.com> References: <1470855666-31696-1-git-send-email-nikunj@linux.vnet.ibm.com> Message-Id: <1470855666-31696-3-git-send-email-nikunj@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH v1 02/10] target-ppc: consolidate load operations List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com, benh@kernel.crashing.org Implement macro to consolidate store operations using newer tcg_gen_qemu_ld functions. Signed-off-by: Nikunj A Dadhania --- target-ppc/translate.c | 70 +++++++++++++++++++------------------------------- 1 file changed, 26 insertions(+), 44 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 2a87d1a..b00da0a 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -2462,50 +2462,32 @@ static inline void gen_align_no_le(DisasContext *ctx) } /*** Integer load ***/ -static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2) -{ - tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx); -} - -static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2) -{ - TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask; - tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); -} - -static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2) -{ - TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask; - tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); -} - -static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2) -{ - TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask; - tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); -} - -static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr) -{ - TCGv tmp = tcg_temp_new(); - gen_qemu_ld32u(ctx, tmp, addr); - tcg_gen_extu_tl_i64(val, tmp); - tcg_temp_free(tmp); -} - -static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) -{ - TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask; - tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); -} - -static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr) -{ - TCGv tmp = tcg_temp_new(); - gen_qemu_ld32s(ctx, tmp, addr); - tcg_gen_ext_tl_i64(val, tmp); - tcg_temp_free(tmp); -} +#define GEN_QEMU_LOAD_TL(ldop, op) \ +static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ + TCGv val, \ + TCGv addr) \ +{ \ + tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, \ + op | ctx->default_tcg_memop_mask); \ +} + +GEN_QEMU_LOAD_TL(ld8u, MO_UB) +GEN_QEMU_LOAD_TL(ld16u, MO_UW) +GEN_QEMU_LOAD_TL(ld16s, MO_SW) +GEN_QEMU_LOAD_TL(ld32u, MO_UL) +GEN_QEMU_LOAD_TL(ld32s, MO_SL) + +#define GEN_QEMU_LOAD_64(ldop, op) \ +static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ + TCGv_i64 val, \ + TCGv addr) \ +{ \ + tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, \ + op | ctx->default_tcg_memop_mask); \ +} + +GEN_QEMU_LOAD_64(ld32u, MO_UL) +GEN_QEMU_LOAD_64(ld32s, MO_SL) static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) { -- 2.7.4