From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37515) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bXYlB-0007Sa-C5 for qemu-devel@nongnu.org; Wed, 10 Aug 2016 15:01:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bXYl2-0008BO-4e for qemu-devel@nongnu.org; Wed, 10 Aug 2016 15:01:49 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:56756) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bXYl1-0008B3-RQ for qemu-devel@nongnu.org; Wed, 10 Aug 2016 15:01:40 -0400 Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id u7AIxMKs029150 for ; Wed, 10 Aug 2016 15:01:39 -0400 Received: from e28smtp06.in.ibm.com (e28smtp06.in.ibm.com [125.16.236.6]) by mx0a-001b2d01.pphosted.com with ESMTP id 24qm9tvapj-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 10 Aug 2016 15:01:38 -0400 Received: from localhost by e28smtp06.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 11 Aug 2016 00:31:35 +0530 From: Nikunj A Dadhania Date: Thu, 11 Aug 2016 00:30:59 +0530 In-Reply-To: <1470855666-31696-1-git-send-email-nikunj@linux.vnet.ibm.com> References: <1470855666-31696-1-git-send-email-nikunj@linux.vnet.ibm.com> Message-Id: <1470855666-31696-4-git-send-email-nikunj@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH v1 03/10] target-ppc: consolidate store operations List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com, benh@kernel.crashing.org Implement macro to consolidate store operations using newer tcg_gen_qemu_st functions. Signed-off-by: Nikunj A Dadhania --- target-ppc/translate.c | 37 ++++++++++++++++++------------------- 1 file changed, 18 insertions(+), 19 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index b00da0a..c7bbe28 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -2495,30 +2495,29 @@ static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op); } -static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2) -{ - tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx); +#define GEN_QEMU_STORE_TL(stop, op) \ +static void glue(gen_qemu_, stop)(DisasContext *ctx, \ + TCGv val, \ + TCGv addr) \ +{ \ + tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, \ + op | ctx->default_tcg_memop_mask); \ } -static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2) -{ - TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask; - tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op); -} +GEN_QEMU_STORE_TL(st8, MO_UB) +GEN_QEMU_STORE_TL(st16, MO_UW) +GEN_QEMU_STORE_TL(st32, MO_UL) -static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2) -{ - TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask; - tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op); +#define GEN_QEMU_STORE_64(stop, op) \ +static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ + TCGv_i64 val, \ + TCGv addr) \ +{ \ + tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, \ + op | ctx->default_tcg_memop_mask); \ } -static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr) -{ - TCGv tmp = tcg_temp_new(); - tcg_gen_trunc_i64_tl(tmp, val); - gen_qemu_st32(ctx, tmp, addr); - tcg_temp_free(tmp); -} +GEN_QEMU_STORE_64(st32, MO_UL) static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) { -- 2.7.4