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From: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net
Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com,
	benh@kernel.crashing.org,
	Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
Subject: [Qemu-devel] [PATCH v3 4/5] target-ppc: add vector bit permute doubleword instruction
Date: Thu, 11 Aug 2016 13:06:47 +0530	[thread overview]
Message-ID: <1470901008-3284-5-git-send-email-raji@linux.vnet.ibm.com> (raw)
In-Reply-To: <1470901008-3284-1-git-send-email-raji@linux.vnet.ibm.com>

Add vbpermd instruction from ISA 3.0.

Signed-off-by: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
---
 target-ppc/helper.h             |    1 +
 target-ppc/int_helper.c         |   22 ++++++++++++++++++++++
 target-ppc/translate/vmx-impl.c |    1 +
 target-ppc/translate/vmx-ops.c  |    1 +
 4 files changed, 25 insertions(+), 0 deletions(-)

diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 6e6e7b3..d1d9418 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -335,6 +335,7 @@ DEF_HELPER_2(vpopcntb, void, avr, avr)
 DEF_HELPER_2(vpopcnth, void, avr, avr)
 DEF_HELPER_2(vpopcntw, void, avr, avr)
 DEF_HELPER_2(vpopcntd, void, avr, avr)
+DEF_HELPER_3(vbpermd, void, avr, avr, avr)
 DEF_HELPER_3(vbpermq, void, avr, avr, avr)
 DEF_HELPER_2(vgbbd, void, avr, avr)
 DEF_HELPER_3(vpmsumb, void, avr, avr, avr)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 162f1e9..6bed3b6 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -1134,6 +1134,28 @@ void helper_vperm(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b,
 #define VBPERMQ_DW(index) (((index) & 0x40) == 0)
 #endif
 
+void helper_vbpermd(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+    int i, j;
+    uint64_t perm = 0;
+    ppc_avr_t result;
+
+    VECTOR_FOR_INORDER_I(i, u64) {
+        perm = 0;
+        for (j = 0; j < 8; j++) {
+            int index = VBPERMQ_INDEX(b, (i * 8) + j);
+            if (index < 64) {
+                uint64_t mask = (1ull << (63 - (index & 0x3F)));
+                if (a->u64[VBPERMQ_DW(index)] & mask) {
+                    perm |= (0x80 >> j);
+                }
+            }
+        }
+        result.u64[i] = perm;
+    }
+    *r = result;
+}
+
 void helper_vbpermq(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
 {
     int i;
diff --git a/target-ppc/translate/vmx-impl.c b/target-ppc/translate/vmx-impl.c
index ebf123f..38f8ad7 100644
--- a/target-ppc/translate/vmx-impl.c
+++ b/target-ppc/translate/vmx-impl.c
@@ -776,6 +776,7 @@ GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
                 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
                 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
+GEN_VXFORM(vbpermd, 6, 23);
 GEN_VXFORM(vbpermq, 6, 21);
 GEN_VXFORM_NOA(vgbbd, 6, 20);
 GEN_VXFORM(vpmsumb, 4, 16)
diff --git a/target-ppc/translate/vmx-ops.c b/target-ppc/translate/vmx-ops.c
index 5b2826e..32bd533 100644
--- a/target-ppc/translate/vmx-ops.c
+++ b/target-ppc/translate/vmx-ops.c
@@ -261,6 +261,7 @@ GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
 GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
 GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
 
+GEN_VXFORM_300(vbpermd, 6, 23),
 GEN_VXFORM_207(vbpermq, 6, 21),
 GEN_VXFORM_207(vgbbd, 6, 20),
 GEN_VXFORM_207(vpmsumb, 4, 16),
-- 
1.7.1

  parent reply	other threads:[~2016-08-11  7:37 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-11  7:36 [Qemu-devel] [PATCH v3 0/5] POWER9 TCG enablement - part3 Rajalakshmi Srinivasaraghavan
2016-08-11  7:36 ` [Qemu-devel] [PATCH v3 1/5] target-ppc: add vector insert instructions Rajalakshmi Srinivasaraghavan
2016-08-16  4:18   ` David Gibson
2016-08-19  5:46     ` Rajalakshmi Srinivasaraghavan
2016-08-23 15:08       ` David Gibson
2016-08-11  7:36 ` [Qemu-devel] [PATCH v3 2/5] target-ppc: add vector extract instructions Rajalakshmi Srinivasaraghavan
2016-08-16  4:21   ` David Gibson
2016-08-11  7:36 ` [Qemu-devel] [PATCH v3 3/5] target-ppc: add vector count trailing zeros instructions Rajalakshmi Srinivasaraghavan
2016-08-16  4:46   ` David Gibson
2016-08-11  7:36 ` Rajalakshmi Srinivasaraghavan [this message]
2016-08-16  4:33   ` [Qemu-devel] [PATCH v3 4/5] target-ppc: add vector bit permute doubleword instruction David Gibson
2016-08-11  7:36 ` [Qemu-devel] [PATCH v3 5/5] target-ppc: add vector permute right indexed instruction Rajalakshmi Srinivasaraghavan
2016-08-16  4:45   ` David Gibson
2016-08-16 10:14     ` Rajalakshmi Srinivasaraghavan

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