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From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net
Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com,
	benh@kernel.crashing.org,
	Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
Subject: [Qemu-devel] [PATCH v2 11/17] target-ppc: implement darn instruction
Date: Sat, 13 Aug 2016 00:04:37 +0530	[thread overview]
Message-ID: <1471026883-27235-12-git-send-email-nikunj@linux.vnet.ibm.com> (raw)
In-Reply-To: <1471026883-27235-1-git-send-email-nikunj@linux.vnet.ibm.com>

From: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>

darn: Deliver A Random Number

Currently return invalid random number for all the case. This needs
proper algorithm to provide cryptographically suitable random data.
Reading from /dev/random can block and that is not an expected behaviour
while the cpu instruction is getting executed. Moreover, /dev/random
would only work for linux-user

Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
 target-ppc/helper.h     |  2 ++
 target-ppc/int_helper.c | 16 ++++++++++++++++
 target-ppc/translate.c  | 18 ++++++++++++++++++
 3 files changed, 36 insertions(+)

diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index dcf3f95..695a2db 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -50,6 +50,8 @@ DEF_HELPER_FLAGS_1(cnttzd, TCG_CALL_NO_RWG_SE, tl, tl)
 DEF_HELPER_FLAGS_1(popcntd, TCG_CALL_NO_RWG_SE, tl, tl)
 DEF_HELPER_FLAGS_2(bpermd, TCG_CALL_NO_RWG_SE, i64, i64, i64)
 DEF_HELPER_3(srad, tl, env, tl, tl)
+DEF_HELPER_0(darn32, tl)
+DEF_HELPER_0(darn64, tl)
 #endif
 
 DEF_HELPER_FLAGS_1(cntlsw32, TCG_CALL_NO_RWG_SE, i32, i32)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 552b2e0..ca33add 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -182,6 +182,22 @@ target_ulong helper_cnttzd(target_ulong t)
 {
     return ctz64(t);
 }
+
+/* Return invalid random number.
+ *
+ * FIXME: Add rng backend or other mechanism to get cryptographically suitable
+ * random number
+ */
+target_ulong helper_darn32(void)
+{
+    return -1;
+}
+
+target_ulong helper_darn64(void)
+{
+    return -1;
+}
+
 #endif
 
 #if defined(TARGET_PPC64)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 89a4b37..2e5116e 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -526,6 +526,8 @@ EXTRACT_HELPER(FPW, 16, 1);
 
 /* addpcis */
 EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
+/* darn */
+EXTRACT_HELPER(L, 16, 2);
 
 /***                            Jump target decoding                       ***/
 /* Immediate address */
@@ -1893,6 +1895,21 @@ static void gen_cnttzd(DisasContext *ctx)
         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
     }
 }
+
+/* darn */
+static void gen_darn(DisasContext *ctx)
+{
+    int l = L(ctx->opcode);
+
+    if (l == 0) {
+        gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
+    } else if (l <= 2) {
+        /* Return 64-bit random for both CRN and RRN */
+        gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
+    } else {
+        tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
+    }
+}
 #endif
 
 /***                             Integer rotate                            ***/
@@ -6207,6 +6224,7 @@ GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300),
 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
 #endif
-- 
2.7.4

  parent reply	other threads:[~2016-08-12 18:35 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-12 18:34 [Qemu-devel] [PATCH v2 00/17] POWER9 TCG enablements - part4 Nikunj A Dadhania
2016-08-12 18:34 ` [Qemu-devel] [PATCH v2 01/17] target-ppc: consolidate load operations Nikunj A Dadhania
2016-08-12 18:34 ` [Qemu-devel] [PATCH v2 02/17] target-ppc: convert ld64 to use new macro Nikunj A Dadhania
2016-08-12 18:34 ` [Qemu-devel] [PATCH v2 03/17] target-ppc: convert ld[16, 32, 64]ur " Nikunj A Dadhania
2016-08-12 18:34 ` [Qemu-devel] [PATCH v2 04/17] target-ppc: consolidate store operations Nikunj A Dadhania
2016-08-12 18:34 ` [Qemu-devel] [PATCH v2 05/17] target-ppc: convert st64 to use new macro Nikunj A Dadhania
2016-08-12 18:34 ` [Qemu-devel] [PATCH v2 06/17] target-ppc: convert st[16, 32, 64]r " Nikunj A Dadhania
2016-08-12 18:34 ` [Qemu-devel] [PATCH v2 07/17] target-ppc: consolidate load with reservation Nikunj A Dadhania
2016-08-12 18:34 ` [Qemu-devel] [PATCH v2 08/17] target-ppc: move out stqcx impementation Nikunj A Dadhania
2016-08-12 18:34 ` [Qemu-devel] [PATCH v2 09/17] target-ppc: consolidate store conditional Nikunj A Dadhania
2016-08-12 18:34 ` [Qemu-devel] [PATCH v2 10/17] target-ppc: add xxspltib instruction Nikunj A Dadhania
2016-08-12 18:34 ` Nikunj A Dadhania [this message]
2016-08-12 18:34 ` [Qemu-devel] [PATCH v2 12/17] target-ppc: add lxsi[bw]zx instruction Nikunj A Dadhania
2016-08-12 18:34 ` [Qemu-devel] [PATCH v2 13/17] target-ppc: add stxsi[bh]x instruction Nikunj A Dadhania
2016-08-12 18:34 ` [Qemu-devel] [PATCH v2 14/17] target-ppc: improve lxvw4x implementation Nikunj A Dadhania
2016-08-12 18:34 ` [Qemu-devel] [PATCH v2 15/17] target-ppc: add lxvb16x and lxvh8x Nikunj A Dadhania
2016-08-12 18:34 ` [Qemu-devel] [PATCH v2 16/17] target-ppc: improve stxvw4x implementation Nikunj A Dadhania
2016-08-12 18:34 ` [Qemu-devel] [PATCH v2 17/17] target-ppc: add stxvb16x and stxvh8x Nikunj A Dadhania
2016-08-17  3:03 ` [Qemu-devel] [PATCH v2 00/17] POWER9 TCG enablements - part4 David Gibson
2016-08-17  4:32   ` Nikunj A Dadhania

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