From: Sergey Sorokin <afarallax@yandex.ru>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, Sergey Sorokin <afarallax@yandex.ru>
Subject: [Qemu-devel] [PATCH] target-arm: Fix lpae bit in FSR on an alignment fault
Date: Mon, 15 Aug 2016 20:48:13 +0300 [thread overview]
Message-ID: <1471283293-169850-1-git-send-email-afarallax@yandex.ru> (raw)
If an alignment fault occurred and target EL is using AArch32,
then DFSR/IFSR bit LPAE[9] must be set correctly.
Signed-off-by: Sergey Sorokin <afarallax@yandex.ru>
---
target-arm/op_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 3e8588e..be27b21 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -194,7 +194,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
* the LPAE long descriptor format, or the short descriptor format
*/
if (arm_s1_regime_using_lpae_format(env, cpu_mmu_index(env, false))) {
- env->exception.fsr = 0x21;
+ env->exception.fsr = (1 << 9) | 0x21;
} else {
env->exception.fsr = 0x1;
}
--
1.9.3
next reply other threads:[~2016-08-15 17:48 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-15 17:48 Sergey Sorokin [this message]
2016-08-15 18:06 ` [Qemu-devel] [PATCH] target-arm: Fix lpae bit in FSR on an alignment fault Peter Maydell
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