From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39597) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bfilI-0000tc-KA for qemu-devel@nongnu.org; Fri, 02 Sep 2016 03:19:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bfilE-0003f8-Hk for qemu-devel@nongnu.org; Fri, 02 Sep 2016 03:19:40 -0400 Message-ID: <1472800761.9620.6.camel@kernel.crashing.org> From: Benjamin Herrenschmidt Date: Fri, 02 Sep 2016 17:19:21 +1000 In-Reply-To: <1472797976-24210-1-git-send-email-nikunj@linux.vnet.ibm.com> References: <1472797976-24210-1-git-send-email-nikunj@linux.vnet.ibm.com> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH RFC 0/4] Enable MTTCG on PowerPC List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Nikunj A Dadhania , qemu-ppc@nongnu.org, alex.bennee@linaro.org, david@gibson.dropbear.id.au, rth@twiddle.net Cc: qemu-devel@nongnu.org On Fri, 2016-09-02 at 12:02 +0530, Nikunj A Dadhania wrote: > The series is a first attempt at enabling Multi-Threaded TCG on PowerPC. > Changes that were needed to enable PowerPC are pretty simple; >=20 > Patch 01: Take a iothread lock during hcall, as hcall can generate io r= equests > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A002: For TCG, we were harcoding smt = as 1, this gets rid of the limitation If we do this, we need to implement the shared SPRs properly and the inter-thread doorbells... > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A003: Use atomic_cmpxchg in store con= ditional > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A004: With more threads, flush the en= try from each cpu.=C2=A0 > =C2=A0=C2=A0This can be optimized further. >=20 > The patches are based on the Alex Bennee's base enabling patches for=C2= =A0 > MTTCG[1] and Emilios's cmpxchg atomics. The consolidated tree of the=C2= =A0 > above patches is here: >=20 > https://github.com/stsquad/qemu/tree/mttcg/base-patches-v4-with-cmpxchg= -atomics-v2 >=20 > Apart from the above, PPC patches are based out of ppc-for-2.8 and=C2=A0 > load/store consolidation patches [2] >=20 > Series with all dependent patches available here:=C2=A0 > https://github.com/nikunjad/qemu/tree/ppc_mttcg_v1 >=20 > Testing:=C2=A0 > =3D=3D=3D=3D=3D=3D=3D=3D >=20 > -smp 4,cores=3D1,threads=3D4 -accel tcg,thread=3Dmulti >=20 > TODO > =3D=3D=3D=3D > Implement msgsndp instructions(door-bell), newer kernels enable it=C2=A0 > depending on the PVR. I have been using following workaround to boot. > https://github.com/nikunjad/qemu/commit/2c10052c5f93418a6b920e6ba3ce181= 3fcf50bc4 >=20 > [1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg391966.html > [2] https://lists.gnu.org/archive/html/qemu-ppc/2016-08/msg00265.html >=20 > Nikunj A Dadhania (4): > =C2=A0 spapr-hcall: take iothread lock during handler call > =C2=A0 target-ppc: with MTTCG report more threads > =C2=A0 target-ppc: use atomic_cmpxchg for ld/st reservation > =C2=A0 target-ppc: flush tlb from all the cpu >=20 > =C2=A0cputlb.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0| 15 +++++++++++++++ > =C2=A0hw/ppc/spapr_hcall.c=C2=A0=C2=A0=C2=A0=C2=A0| 11 +++++++++-- > =C2=A0include/exec/exec-all.h |=C2=A0=C2=A02 ++ > =C2=A0target-ppc/kvm.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0|= =C2=A0=C2=A02 +- > =C2=A0target-ppc/kvm_ppc.h=C2=A0=C2=A0=C2=A0=C2=A0|=C2=A0=C2=A02 +- > =C2=A0target-ppc/mmu-hash64.c |=C2=A0=C2=A02 +- > =C2=A0target-ppc/translate.c=C2=A0=C2=A0| 24 +++++++++++++++++++++--- > =C2=A07 files changed, 50 insertions(+), 8 deletions(-) >=20